BIT2
#define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT2
#define WIFI_HS_CONNECTED BIT2
#define INTF_NOTIFY BIT2
#define ALGO_BT_MONITOR BIT2
#define WOW_MAGIC BIT2 /* Magic packet */
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
#define RESET_DONE BIT2
#define OVER_RUN BIT2
#define RESET_DEV0 BIT2
#define WIDE_NEGO_ENABLE BIT2
#define RST_SCSI_BUS BIT2
#define FORMATING_MEDIA BIT2
#define ASPI_SUPPORT BIT2
#define LPFC_SLI4_INTR2 BIT2
BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2 + BIT3);
p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2);
BIT7 + BIT2 + BIT1 + BIT0);
(viafb_read_reg(VIASR, SR1E) & BIT2) >> 2;
reg_val << 2, BIT2);