BIT1
if ((coex_sta->bt_info_ext & BIT1)) {
#define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT0 | BIT1);
if (coex_sta->bt_info_ext & BIT1) {
#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT0 | BIT1);
if ((coex_sta->bt_info_ext & BIT1)) {
#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
if (coex_sta->bt_info_ext & BIT1) {
#define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT1
if ((coex_sta->bt_info_ext & BIT1)) {
#define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1
#define WIFI_AP_CONNECTED BIT1
#define ALGO_WIFI_RSSI_STATE BIT1
#define WOW_WOMEN BIT1 /* WoW function on or off. */
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
#define RESET_DETECT BIT1
#define ABORTION BIT1
#define ABORT_DEV BIT1
#define SYNC_NEGO_DONE BIT1
#define GREATER_1G BIT1
#define UNIT_INFO_CHANGED BIT1
#define SCSI_SUPPORT BIT1
#define LPFC_SLI4_INTR1 BIT1
viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2 + BIT3);
viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2 + BIT3);
viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2);
viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
BIT7 + BIT2 + BIT1 + BIT0);
viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1);
(viafb_read_reg(VIASR, SR1B) & BIT1) >> 1;
reg_val << 1, BIT1);