BIT0
h2c_parameter[0] |= BIT0; /* function enable */
u8tmp |= BIT0;
u8tmp |= BIT0;
(bt_info_ext&BIT0) ? "Basic rate" : "EDR rate");
h2c_parameter[0] |= BIT0; /* trigger */
h2c_parameter[0] |= BIT0;
#define BT_INFO_8192E_2ANT_B_CONNECTION BIT0
btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT0 | BIT1);
(bt_info_ext & BIT0) ? "Basic rate" : "EDR rate");
h2c_parameter[1] |= BIT0;
h2c_parameter[0] |= BIT0; /* function enable */
#define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
(((_BT_INFO_EXT_&BIT0)) ? true : false)
h2c_parameter[0] |= BIT0; /* trigger */
btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT0 | BIT1);
(bt_info_ext & BIT0) ? "Basic rate" : "EDR rate");
h2c_parameter[1] |= BIT0;
h2c_parameter[0] |= BIT0; /* function enable */
#define BT_INFO_8723B_2ANT_B_CONNECTION BIT0
(bt_info_ext & BIT0) ?
h2c_parameter[0] |= BIT0; /* trigger */
h2c_parameter[1] |= BIT0;
h2c_parameter[0] |= BIT0; /* function enable */
#define BT_INFO_8821A_1ANT_B_CONNECTION BIT0
(((_BT_INFO_EXT_&BIT0)) ? true : false)
h2c_parameter[0] |= BIT0; /* trigger */
(bt_info_ext&BIT0) ? "Basic rate" : "EDR rate");
h2c_parameter[1] |= BIT0;
h2c_parameter[0] |= BIT0; /* function enable */
#define BT_INFO_8821A_2ANT_B_CONNECTION BIT0
#define WIFI_STA_CONNECTED BIT0
#define INTF_INIT BIT0
#define ALGO_BT_RSSI_STATE BIT0
#define WOW_PMEN BIT0 /* Power management Enable. */
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1 \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
#define RESET_DEV BIT0
#define ABORT_DEV_ BIT0
#define SRB_OK BIT0
#define AUTO_REQSENSE BIT0
#define SYNC_NEGO_ENABLE BIT0
#define MORE2_DRV BIT0
#define UNIT_ALLOCATED BIT0
#define DASD_SUPPORT BIT0
#define LPFC_SLI4_INTR0 BIT0
#define BIT_FA_RESET BIT0
BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2 + BIT3);
viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2 + BIT3);
viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);
viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
reg_mask = reg_mask | (BIT0 << j);
get_bit = (timing_value & (BIT0 << bit_num));
viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2);
viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
BIT7 + BIT2 + BIT1 + BIT0);
bdithering = BIT0;
viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);