TEGRA124_MC_RESET
TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),