TGT
} else if (bus == TGT) {
grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, tmp);
} else if (bus == TGT) {
grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
grpci1_cfg_r32(priv, TGT, 0, PCI_BASE_ADDRESS_0, &bar_sz);
grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, pciadr);
grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_1, ahbadr);
grpci1_cfg_w8(priv, TGT, 0, PCI_CACHE_LINE_SIZE, 0xff);
grpci1_cfg_w8(priv, TGT, 0, PCI_LATENCY_TIMER, 0x40);
grpci1_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data);
grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, data);
grpci1_cfg_r16(priv, TGT, 0, PCI_STATUS, &status);
grpci1_cfg_w16(priv, TGT, 0, PCI_STATUS, status);
} else if (bus == TGT) {
} else if (bus == TGT) {
grpci2_cfg_r32(priv, TGT, 0, PCI_VENDOR_ID, &priv->pciid);
grpci2_cfg_r8(priv, TGT, 0, PCI_CAPABILITY_LIST, &capptr);
grpci2_cfg_r32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, &io_map);
grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, io_map);
grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BARSIZE_OFS+i*4,
grpci2_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr);
grpci2_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data);
grpci2_cfg_w32(priv, TGT, 0, PCI_COMMAND, data);
#define BPF_CALL_REL(TGT) \
.imm = TGT })
#define BPF_CALL_REL(TGT) \
.imm = TGT })