TGA_WRITE_REG
TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
TGA_WRITE_REG(par, deep_presets[tga_type] |
TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);
TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG);
TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG);
TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, BT459_ADDR_LO << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, a & 0xff, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, BT459_ADDR_HI << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, a >> 8, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, v, TGA_RAMDAC_REG);