TG3_BDINFO_SIZE
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
txrcb < limit; txrcb += TG3_BDINFO_SIZE)
for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {