drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
185
TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
186
TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
187
TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
188
TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
189
TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
190
TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
191
TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
192
TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
193
TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
194
TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
195
TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
196
TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
197
TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
198
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
199
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
200
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
201
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
202
TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
203
TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
204
TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
205
TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
206
TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
208
TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
209
TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
210
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
211
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
212
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
213
TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
214
TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
215
TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
216
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
217
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
218
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
219
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
220
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
221
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
222
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
223
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
224
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
225
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
226
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
227
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
228
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
229
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
230
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
231
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
232
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
233
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
234
TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
235
TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
236
TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
237
TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
238
TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
239
TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
240
TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
241
TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
242
TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
243
TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
244
TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
245
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
246
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
247
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
248
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
249
TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
250
TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
251
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
252
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
253
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
254
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
255
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
256
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
257
TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
258
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
259
TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
260
TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
261
TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
262
TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
263
TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
264
TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
265
TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
266
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
267
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
268
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
269
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
270
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
271
TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
272
TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
273
TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
274
TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
275
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
276
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
277
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
278
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
279
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
280
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
281
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
282
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
283
TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
284
TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
285
TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
286
TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
287
TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
288
TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
289
TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
290
TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
291
TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
292
TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
293
TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
294
TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
295
TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
296
TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
297
TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
298
TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
299
TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
300
TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
301
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
302
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
303
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
304
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
305
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
306
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
307
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
308
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
309
TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
310
TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
311
TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
312
TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
313
TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
314
TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
315
TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
316
TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
317
TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
318
TF_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
319
TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
320
TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
321
TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
322
TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
323
TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
324
TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
325
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
327
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
328
TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
329
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
330
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
331
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
332
TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
333
TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
334
TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
335
TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
336
TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
337
TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh)
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
341
TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
342
TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
343
TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
344
TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
345
TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
346
TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
347
TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
348
TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
349
TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
350
TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
351
TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
352
TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
353
TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
354
TF_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
355
TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
356
TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
357
TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
358
TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
359
TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
360
TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
361
TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
362
TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_SCALE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
363
TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_SCALE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
364
TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_SCALE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
365
TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
366
TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
367
TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
368
TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
369
TF_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
370
TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
371
TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
372
TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
373
TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
374
TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
375
TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
376
TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
377
TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
378
TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
379
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
380
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
381
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
382
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
383
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
384
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
385
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
386
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
387
TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
388
TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
389
TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
390
TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
391
TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
392
TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
393
TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
394
TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
395
TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
396
TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
397
TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
398
TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
399
TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
400
TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
401
TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
402
TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
403
TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
404
TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
405
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
406
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
407
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
408
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
409
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
410
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
411
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
412
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
413
TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
414
TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
415
TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
416
TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
417
TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
418
TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
419
TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
420
TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
421
TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
422
TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
423
TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
424
TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
425
TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
426
TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
427
TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
428
TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
429
TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
430
TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
431
TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
432
TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
433
TF_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
434
TF_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
435
TF_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
436
TF_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
437
TF_SF(CM0_CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
438
TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
439
TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
440
TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
441
TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
442
TF_SF(DPP_TOP0_DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
186
TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
187
TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
188
TF_SF(CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
189
TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
190
TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
191
TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
192
TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
193
TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
194
TF_SF(CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
195
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
196
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
197
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
198
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
199
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
200
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
201
TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_LUT_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
202
TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_EN_MASK, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
203
TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_LUT_WRITE_SEL, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
204
TF_SF(CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK, CM_BLNDGAM_CONFIG_STATUS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
205
TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh)
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
209
TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
210
TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
211
TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
212
TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
213
TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
214
TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
215
TF_SF(CM0_CM_BLNDGAM_RAMB_START_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
216
TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_B, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
217
TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_G, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
218
TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL2_R, CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
219
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
220
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
221
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
222
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_0_1, CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
223
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
224
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
225
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
226
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_2_3, CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
227
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
228
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
229
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
230
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_4_5, CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
231
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
232
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
233
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
234
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_6_7, CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
235
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
236
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
237
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
238
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_8_9, CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
239
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
240
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
241
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
242
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_10_11, CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
243
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
244
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
245
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
246
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_12_13, CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
247
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
248
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
249
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
250
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_14_15, CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
251
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
252
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
253
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
254
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_16_17, CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
255
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
256
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
257
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
258
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_18_19, CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
259
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
260
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
261
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
262
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_20_21, CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
263
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
264
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
265
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
266
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_22_23, CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
267
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
268
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
269
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
270
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_24_25, CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
271
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
272
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
273
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
274
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_26_27, CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
275
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
276
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
277
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
278
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_28_29, CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
279
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
280
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
281
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
282
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_30_31, CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
283
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
284
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
285
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
286
TF_SF(CM0_CM_BLNDGAM_RAMB_REGION_32_33, CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
287
TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
288
TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
289
TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
290
TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
291
TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
292
TF_SF(CM0_CM_BLNDGAM_RAMA_START_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
293
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
294
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
295
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
296
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
297
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
298
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
299
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_0_1, CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
300
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
301
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
302
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
303
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_2_3, CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
304
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
305
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
306
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
307
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_4_5, CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
308
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
309
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
310
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
311
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_6_7, CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
312
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
313
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
314
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
315
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_8_9, CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
316
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
317
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
318
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
319
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_10_11, CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
320
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
321
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
322
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
323
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_12_13, CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
324
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
325
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
326
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
327
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_14_15, CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
328
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
329
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
330
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
331
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_16_17, CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
332
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
333
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
334
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
335
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_18_19, CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
336
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
337
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
338
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
339
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_20_21, CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
340
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
341
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
342
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
343
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_22_23, CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
344
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
345
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
346
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
347
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_24_25, CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
348
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
349
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
350
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
351
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_26_27, CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
352
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
353
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
354
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
355
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_28_29, CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
356
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
357
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
358
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
359
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_30_31, CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
360
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
361
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
362
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
363
TF_SF(CM0_CM_BLNDGAM_RAMA_REGION_32_33, CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
364
TF_SF(CM0_CM_BLNDGAM_LUT_INDEX, CM_BLNDGAM_LUT_INDEX, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
365
TF_SF(CM0_CM_BLNDGAM_LUT_DATA, CM_BLNDGAM_LUT_DATA, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
366
TF_SF(CM0_CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
367
TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
368
TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_SIZE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
369
TF_SF(CM0_CM_3DLUT_INDEX, CM_3DLUT_INDEX, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
370
TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA0, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
371
TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA1, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
372
TF_SF(CM0_CM_3DLUT_DATA_30BIT, CM_3DLUT_DATA_30BIT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
373
TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
374
TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_RAM_SEL, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
375
TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
376
TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_READ_SEL, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
377
TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_LUT_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
378
TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
379
TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
380
TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_START_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
381
TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
382
TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_START_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
383
TF_SF(CM0_CM_SHAPER_RAMB_START_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
384
TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_END_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
385
TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_B, CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
386
TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_END_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
387
TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_G, CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
388
TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_END_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
389
TF_SF(CM0_CM_SHAPER_RAMB_END_CNTL_R, CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
390
TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
391
TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
392
TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
393
TF_SF(CM0_CM_SHAPER_RAMB_REGION_0_1, CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
394
TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
395
TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
396
TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
397
TF_SF(CM0_CM_SHAPER_RAMB_REGION_2_3, CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
398
TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
399
TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
400
TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
401
TF_SF(CM0_CM_SHAPER_RAMB_REGION_4_5, CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
402
TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
403
TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
404
TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
405
TF_SF(CM0_CM_SHAPER_RAMB_REGION_6_7, CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
406
TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
407
TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
408
TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
409
TF_SF(CM0_CM_SHAPER_RAMB_REGION_8_9, CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
410
TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
411
TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
412
TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
413
TF_SF(CM0_CM_SHAPER_RAMB_REGION_10_11, CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
414
TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
415
TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
416
TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
417
TF_SF(CM0_CM_SHAPER_RAMB_REGION_12_13, CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
418
TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
419
TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
420
TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
421
TF_SF(CM0_CM_SHAPER_RAMB_REGION_14_15, CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
422
TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
423
TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
424
TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
425
TF_SF(CM0_CM_SHAPER_RAMB_REGION_16_17, CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
426
TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
427
TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
428
TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
429
TF_SF(CM0_CM_SHAPER_RAMB_REGION_18_19, CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
430
TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
431
TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
432
TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
433
TF_SF(CM0_CM_SHAPER_RAMB_REGION_20_21, CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
434
TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
435
TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
436
TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
437
TF_SF(CM0_CM_SHAPER_RAMB_REGION_22_23, CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
438
TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
439
TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
440
TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
441
TF_SF(CM0_CM_SHAPER_RAMB_REGION_24_25, CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
442
TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
443
TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
444
TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
445
TF_SF(CM0_CM_SHAPER_RAMB_REGION_26_27, CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
446
TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
447
TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
448
TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
449
TF_SF(CM0_CM_SHAPER_RAMB_REGION_28_29, CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
450
TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
451
TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
452
TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
453
TF_SF(CM0_CM_SHAPER_RAMB_REGION_30_31, CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
454
TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
455
TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
456
TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
457
TF_SF(CM0_CM_SHAPER_RAMB_REGION_32_33, CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
458
TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_START_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
459
TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
460
TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_START_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
461
TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
462
TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_START_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
463
TF_SF(CM0_CM_SHAPER_RAMA_START_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
464
TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_END_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
465
TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_B, CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
466
TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_END_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
467
TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_G, CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
468
TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_END_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
469
TF_SF(CM0_CM_SHAPER_RAMA_END_CNTL_R, CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
470
TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
471
TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
472
TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
473
TF_SF(CM0_CM_SHAPER_RAMA_REGION_0_1, CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
474
TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
475
TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
476
TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
477
TF_SF(CM0_CM_SHAPER_RAMA_REGION_2_3, CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
478
TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
479
TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
480
TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
481
TF_SF(CM0_CM_SHAPER_RAMA_REGION_4_5, CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
482
TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
483
TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
484
TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
485
TF_SF(CM0_CM_SHAPER_RAMA_REGION_6_7, CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
486
TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
487
TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
488
TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
489
TF_SF(CM0_CM_SHAPER_RAMA_REGION_8_9, CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
490
TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
491
TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
492
TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
493
TF_SF(CM0_CM_SHAPER_RAMA_REGION_10_11, CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
494
TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
495
TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
496
TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
497
TF_SF(CM0_CM_SHAPER_RAMA_REGION_12_13, CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
498
TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
499
TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
500
TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
501
TF_SF(CM0_CM_SHAPER_RAMA_REGION_14_15, CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
502
TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
503
TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
504
TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
505
TF_SF(CM0_CM_SHAPER_RAMA_REGION_16_17, CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
506
TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
507
TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
508
TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
509
TF_SF(CM0_CM_SHAPER_RAMA_REGION_18_19, CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
510
TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
511
TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
512
TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
513
TF_SF(CM0_CM_SHAPER_RAMA_REGION_20_21, CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
514
TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
515
TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
516
TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
517
TF_SF(CM0_CM_SHAPER_RAMA_REGION_22_23, CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
518
TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
519
TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
520
TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
521
TF_SF(CM0_CM_SHAPER_RAMA_REGION_24_25, CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
522
TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
523
TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
524
TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
525
TF_SF(CM0_CM_SHAPER_RAMA_REGION_26_27, CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
526
TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
527
TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
528
TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
529
TF_SF(CM0_CM_SHAPER_RAMA_REGION_28_29, CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
530
TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
531
TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
532
TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
533
TF_SF(CM0_CM_SHAPER_RAMA_REGION_30_31, CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
534
TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
535
TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
536
TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
537
TF_SF(CM0_CM_SHAPER_RAMA_REGION_32_33, CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
538
TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_EN_MASK, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
539
TF_SF(CM0_CM_SHAPER_LUT_WRITE_EN_MASK, CM_SHAPER_LUT_WRITE_SEL, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
540
TF_SF(CM0_CM_SHAPER_LUT_INDEX, CM_SHAPER_LUT_INDEX, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
541
TF_SF(CM0_CM_SHAPER_LUT_DATA, CM_SHAPER_LUT_DATA, mask_sh)
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
548
TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
549
TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
550
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
551
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
552
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
553
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
554
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
555
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
556
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
557
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
558
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
559
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
560
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
561
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
562
TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
563
TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
564
TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
565
TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
566
TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
567
TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
568
TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
569
TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
570
TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
571
TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
572
TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
573
TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
574
TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
575
TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
576
TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
577
TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
578
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
579
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
580
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
581
TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h
582
TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh)
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
179
TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
180
TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
181
TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_ABLND, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
182
TF_SF(CM0_CM_BIAS_CR_R, CM_BIAS_CR_R, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
183
TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_Y_G, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
184
TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_CB_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
185
TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
186
TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
187
TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
188
TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_SELECT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
189
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
190
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
191
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_PWL_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
192
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
193
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
194
TF_SF(CM0_CM_GAMCOR_LUT_INDEX, CM_GAMCOR_LUT_INDEX, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
195
TF_SF(CM0_CM_GAMCOR_LUT_DATA, CM_GAMCOR_LUT_DATA, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
196
TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_WRITE_COLOR_MASK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
197
TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_COLOR_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
198
TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_HOST_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
199
TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_CONFIG_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
200
TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
201
TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
202
TF_SF(CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
203
TF_SF(CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
204
TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL1_B, CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
205
TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
206
TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
207
TF_SF(CM0_CM_GAMCOR_RAMA_OFFSET_B, CM_GAMCOR_RAMA_OFFSET_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
208
TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
209
TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
210
TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
211
TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
212
TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
213
TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
214
TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
215
TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
216
TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
217
TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
218
TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
219
TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
220
TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
221
TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
222
TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
223
TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
224
TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
225
TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
226
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
227
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
228
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
229
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
230
TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
231
TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
232
TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
233
TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
234
TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
236
TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
237
TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
238
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
239
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
240
TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
241
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
242
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
243
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
244
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
245
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
246
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
247
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
248
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
249
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
250
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
251
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
252
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
253
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
254
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
255
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
256
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
257
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
258
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
259
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
260
TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
261
TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
262
TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
263
TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
264
TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
265
TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
266
TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
267
TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
268
TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
269
TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
270
TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
271
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
272
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
273
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
274
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
275
TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
276
TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
277
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
278
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
279
TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
280
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
281
TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
282
TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_ABLND_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
283
TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
284
TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_ABLND_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
285
TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
286
TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE_CURRENT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
287
TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C11, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
288
TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C12, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
289
TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C33, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
290
TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C34, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
291
TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
292
TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE_CURRENT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
293
TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C11, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
294
TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C12, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
295
TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C33, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
296
TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C34, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
297
TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
298
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
300
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
301
TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
302
TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_ALPHA_PLANE_ENABLE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
303
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
304
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
305
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
306
TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
307
TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
308
TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
309
TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
310
TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
311
TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
312
TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
313
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
314
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
315
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
316
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
317
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
318
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
319
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
320
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
321
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
322
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
323
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
324
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
325
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
326
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
327
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
328
TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
329
TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
330
TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
331
TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
332
TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
333
TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
334
TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
335
TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
336
TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
337
TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
338
TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
339
TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
340
TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
341
TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
342
TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
343
TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
344
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
345
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
346
TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
347
TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
348
TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
349
TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh)
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
352
TF_SF(CM0_CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
353
TF_SF(CM0_CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
354
TF_SF(CM0_CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
355
TF_SF(CM0_CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
356
TF_SF(CM0_CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
357
TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
358
TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
359
TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
360
TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
361
TF_SF(CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
362
TF_SF(CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
363
TF_SF(CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
364
TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
365
TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
366
TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
367
TF_SF(CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
368
TF_SF(CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
369
TF_SF(CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
370
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
371
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
372
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
373
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
374
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
375
TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
376
TF_SF(CM0_CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
377
TF_SF(CM0_CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_HOST_SEL, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
378
TF_SF(CM0_CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_CONFIG_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
379
TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
380
TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, mask_sh)
drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h
34
TF_SF(DPP_TOP0_DPP_CONTROL, DPP_FGCG_REP_DIS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h
35
TF_SF(DPP_TOP0_DPP_CONTROL, DPP_FGCG_REP_DIS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h
36
TF_SF(DPP_TOP0_DPP_CONTROL, DISPCLK_R_GATE_DISABLE, mask_sh)
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
100
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
101
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
102
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
103
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
104
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
105
TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
106
TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
107
TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
108
TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
109
TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
110
TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
111
TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
112
TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
113
TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
114
TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
115
TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
116
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
117
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
118
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
119
TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
120
TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
121
TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
122
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
123
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
124
TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
125
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
126
TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
127
TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_ABLND_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
128
TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
129
TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_ABLND_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
130
TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
131
TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE_CURRENT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
132
TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C11, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
133
TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C12, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
134
TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C33, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
135
TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C34, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
136
TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
137
TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE_CURRENT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
138
TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C11, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
139
TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C12, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
140
TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C33, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
141
TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C34, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
142
TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
143
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
145
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
146
TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
147
TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_ALPHA_PLANE_ENABLE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
148
TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
149
TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
150
TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
151
TF_SF(CM_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
152
TF_SF(CM_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
153
TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_BIAS_G_Y, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
154
TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_SCALE_G_Y, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
155
TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_BIAS_RB_CRCB, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
156
TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_SCALE_RB_CRCB, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
157
TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
158
TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_MODE_CURRENT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
159
TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_COEF_FORMAT, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
160
TF_SF(CM_CUR0_CUR0_MATRIX_C11_C12_A, CUR0_MATRIX_C11_A, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
161
TF_SF(CM_CUR0_CUR0_MATRIX_C11_C12_A, CUR0_MATRIX_C12_A, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
162
TF_SF(CM_CUR0_CUR0_MATRIX_C13_C14_A, CUR0_MATRIX_C13_A, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
163
TF_SF(CM_CUR0_CUR0_MATRIX_C13_C14_A, CUR0_MATRIX_C14_A, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
164
TF_SF(CM_CUR0_CUR0_MATRIX_C21_C22_A, CUR0_MATRIX_C21_A, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
165
TF_SF(CM_CUR0_CUR0_MATRIX_C21_C22_A, CUR0_MATRIX_C22_A, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
166
TF_SF(CM_CUR0_CUR0_MATRIX_C23_C24_A, CUR0_MATRIX_C23_A, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
167
TF_SF(CM_CUR0_CUR0_MATRIX_C23_C24_A, CUR0_MATRIX_C24_A, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
168
TF_SF(CM_CUR0_CUR0_MATRIX_C31_C32_A, CUR0_MATRIX_C31_A, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
169
TF_SF(CM_CUR0_CUR0_MATRIX_C31_C32_A, CUR0_MATRIX_C32_A, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
170
TF_SF(CM_CUR0_CUR0_MATRIX_C33_C34_A, CUR0_MATRIX_C33_A, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
171
TF_SF(CM_CUR0_CUR0_MATRIX_C33_C34_A, CUR0_MATRIX_C34_A, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
172
TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
173
TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
174
TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
175
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
176
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
177
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
178
TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
179
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
180
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
181
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
182
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
183
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
184
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
185
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
186
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
187
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
188
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
189
TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
190
TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
191
TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
192
TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
193
TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
194
TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
195
TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
196
TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
197
TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, LUMA_KEYER_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
198
TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
199
TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
200
TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
201
TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
202
TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
203
TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
204
TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
205
TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
206
TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
207
TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
208
TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
209
TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
210
TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
211
TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
212
TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_DIS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
213
TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
214
TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_MATRIX_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
215
TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_LTONL_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
216
TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
217
TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_RINGEST_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
218
TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_2TAP_SHARP_FACTOR, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
219
TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
220
TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
221
TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF3_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
222
TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_FLAT1_GAIN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
223
TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_FLAT2_GAIN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
224
TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_ROC_GAIN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
225
TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
226
TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
227
TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN, SCL_EASF_H_RINGEST_EVENTAP_GAIN1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
228
TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN, SCL_EASF_H_RINGEST_EVENTAP_GAIN2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
229
TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MAXA, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
230
TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MAXB, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
231
TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MINA, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
232
TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MINB, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
233
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_IN_SEG0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
234
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_BASE_SEG0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
235
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_SLOPE_SEG0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
236
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_IN_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
237
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_BASE_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
238
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_SLOPE_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
239
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_IN_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
240
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_BASE_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
241
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_SLOPE_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
242
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_IN_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
243
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_BASE_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
244
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_SLOPE_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
245
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_IN_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
246
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_BASE_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
247
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_SLOPE_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
248
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_IN_SEG5, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
249
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_BASE_SEG5, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
250
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_SLOPE_SEG5, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
251
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_IN_SEG6, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
252
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_BASE_SEG6, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
253
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_SLOPE_SEG6, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
254
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG7, SCL_EASF_H_BF1_PWL_IN_SEG7, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
255
TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG7, SCL_EASF_H_BF1_PWL_BASE_SEG7, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
256
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_IN_SEG0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
257
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_BASE_SEG0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
258
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_SLOPE_SEG0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
259
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_IN_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
260
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_BASE_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
261
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_SLOPE_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
262
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_IN_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
263
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_BASE_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
264
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_SLOPE_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
265
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_IN_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
266
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_BASE_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
267
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_SLOPE_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
268
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_IN_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
269
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_BASE_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
270
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_SLOPE_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
271
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG5, SCL_EASF_H_BF3_PWL_IN_SEG5, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
272
TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG5, SCL_EASF_H_BF3_PWL_BASE_SEG5, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
273
TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
274
TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_RINGEST_FORCE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
275
TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_2TAP_SHARP_FACTOR, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
276
TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF1_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
277
TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
278
TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF3_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
279
TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_FLAT1_GAIN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
280
TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_FLAT2_GAIN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
281
TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_ROC_GAIN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
282
TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1, SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
283
TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1, SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
284
TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2, SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
285
TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2, SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
286
TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3, SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
287
TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3, SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
288
TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
289
TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
290
TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN, SCL_EASF_V_RINGEST_EVENTAP_GAIN1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
291
TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN, SCL_EASF_V_RINGEST_EVENTAP_GAIN2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
292
TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MAXA, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
293
TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MAXB, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
294
TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MINA, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
295
TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MINB, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
296
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_IN_SEG0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
297
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_BASE_SEG0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
298
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_SLOPE_SEG0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
299
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_IN_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
300
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_BASE_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
301
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_SLOPE_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
302
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_IN_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
303
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_BASE_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
304
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_SLOPE_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
305
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_IN_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
306
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_BASE_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
307
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_SLOPE_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
308
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_IN_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
309
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_BASE_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
310
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_SLOPE_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
311
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_IN_SEG5, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
312
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_BASE_SEG5, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
313
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_SLOPE_SEG5, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
314
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_IN_SEG6, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
315
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_BASE_SEG6, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
316
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_SLOPE_SEG6, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
317
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG7, SCL_EASF_V_BF1_PWL_IN_SEG7, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
318
TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG7, SCL_EASF_V_BF1_PWL_BASE_SEG7, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
319
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_IN_SEG0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
320
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_BASE_SEG0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
321
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_SLOPE_SEG0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
322
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_IN_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
323
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_BASE_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
324
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_SLOPE_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
325
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_IN_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
326
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_BASE_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
327
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_SLOPE_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
328
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_IN_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
329
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_BASE_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
330
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_SLOPE_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
331
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_IN_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
332
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_BASE_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
333
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_SLOPE_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
334
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG5, SCL_EASF_V_BF3_PWL_IN_SEG5, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
335
TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG5, SCL_EASF_V_BF3_PWL_BASE_SEG5, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
336
TF_SF(DSCL0_DSCL_SC_MATRIX_C0C1, SCL_SC_MATRIX_C0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
337
TF_SF(DSCL0_DSCL_SC_MATRIX_C0C1, SCL_SC_MATRIX_C1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
338
TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
339
TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
340
TF_SF(DSCL0_ISHARP_DELTA_CTRL, ISHARP_DELTA_LUT_HOST_SELECT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
341
TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_DIS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
342
TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_FORCE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
343
TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_STATE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
344
TF_SF(DSCL0_ISHARP_DELTA_DATA, ISHARP_DELTA_DATA, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
345
TF_SF(DSCL0_ISHARP_DELTA_INDEX, ISHARP_DELTA_INDEX, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
346
TF_SF(DSCL0_ISHARP_MODE, ISHARP_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
347
TF_SF(DSCL0_ISHARP_MODE, ISHARP_NOISEDET_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
348
TF_SF(DSCL0_ISHARP_MODE, ISHARP_NOISEDET_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
349
TF_SF(DSCL0_ISHARP_MODE, ISHARP_LBA_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
350
TF_SF(DSCL0_ISHARP_MODE, ISHARP_DELTA_LUT_SELECT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
351
TF_SF(DSCL0_ISHARP_MODE, ISHARP_FMT_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
352
TF_SF(DSCL0_ISHARP_MODE, ISHARP_FMT_NORM, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
353
TF_SF(DSCL0_ISHARP_MODE, ISHARP_DELTA_LUT_SELECT_CURRENT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
354
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_IN_SEG0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
355
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_BASE_SEG0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
356
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_SLOPE_SEG0, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
357
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_IN_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
358
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_BASE_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
359
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_SLOPE_SEG1, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
36
TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
360
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_IN_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
361
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_BASE_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
362
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_SLOPE_SEG2, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
363
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_IN_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
364
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_BASE_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
365
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_SLOPE_SEG3, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
366
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_IN_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
367
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_BASE_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
368
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_SLOPE_SEG4, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
369
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG5, ISHARP_LBA_PWL_IN_SEG5, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
37
TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
370
TF_SF(DSCL0_ISHARP_LBA_PWL_SEG5, ISHARP_LBA_PWL_BASE_SEG5, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
371
TF_SF(DSCL0_ISHARP_NOISEDET_THRESHOLD, ISHARP_NOISEDET_UTHRE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
372
TF_SF(DSCL0_ISHARP_NOISEDET_THRESHOLD, ISHARP_NOISEDET_DTHRE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
373
TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_START_IN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
374
TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_END_IN, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
375
TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_SLOPE, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
376
TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_EN_P, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
377
TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_PIVOT_P, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
378
TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_SLOPE_P, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
379
TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_EN_N, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
38
TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_ABLND, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
380
TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_PIVOT_N, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
381
TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_SLOPE_N, mask_sh), \
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
382
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
383
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
384
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
385
TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh)
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
39
TF_SF(CM0_CM_BIAS_CR_R, CM_BIAS_CR_R, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
40
TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_Y_G, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
41
TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_CB_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
42
TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
43
TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
44
TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
45
TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
46
TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_SELECT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
47
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
48
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
49
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_PWL_DISABLE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
50
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
51
TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
52
TF_SF(CM0_CM_GAMCOR_LUT_INDEX, CM_GAMCOR_LUT_INDEX, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
53
TF_SF(CM0_CM_GAMCOR_LUT_DATA, CM_GAMCOR_LUT_DATA, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
54
TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_WRITE_COLOR_MASK, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
55
TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_COLOR_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
56
TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_DBG, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
57
TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_HOST_SEL, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
58
TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_CONFIG_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
59
TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
60
TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
61
TF_SF(CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
62
TF_SF(CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
63
TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL1_B, CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
64
TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
65
TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
66
TF_SF(CM0_CM_GAMCOR_RAMA_OFFSET_B, CM_GAMCOR_RAMA_OFFSET_B, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
67
TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
68
TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
69
TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
70
TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
71
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
72
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
73
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
74
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
75
TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
76
TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
77
TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
78
TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
79
TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
81
TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
82
TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
83
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
84
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
85
TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
86
TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
87
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
88
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
89
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
90
TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
91
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
92
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
93
TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
94
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
95
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
96
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
97
TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
98
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
99
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\
