BIT_9
#define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
#define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_9
#define QLC_83XX_100_CAPABLE BIT_9
#define QLCNIC_ENABLE_IPV6_LRO (BIT_1 | BIT_9)
if (status & BIT_9)
#define ISP_FLASH_UPPER BIT_9 /* Flash upper bank select */
#define TP_STOP_QUEUE BIT_9 /* Stop que on check condition */
#define SF_GOT_TARGET BIT_9 /* */
if (!(mpi_state & BIT_9 && mpi_state & BIT_8 && mpi_state & BIT_15)) {
#define FO1_AE_AUTO_BYPASS BIT_9
#define MBX_9 BIT_9
#define PO_DIS_FRAME_MODE BIT_9
#define SS_SENSE_LEN_VALID BIT_9
#define NVME_PRLI_SP_PI_CTRL BIT_9
#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
#define RDP_PORT_SPEED_32GB BIT_9
#define SRB_EDIF_CLEANUP_DELETE BIT_9
#define DT_ISP5422 BIT_9
#define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
#define CF_EN_EDIF BIT_9
#define TMF_ABORT_TASK_SET BIT_9
#define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */
templates = (risc_attr & BIT_9) ? 2 : 1;
templates = (risc_attr & BIT_9) ? 2 : 1;
templates = (risc_attr & BIT_9) ? 2 : 1;
pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
if (ha->fw_attributes & BIT_9) {
if (risc_attr & BIT_9) {
nv->firmware_options_1 &= cpu_to_le32(~BIT_9);
nv->firmware_options_1 &= cpu_to_le32(~BIT_9);
TRC_SRR_CTIO = BIT_9,
#define OF_FAST_POST BIT_9 /* Enable mailbox fast posting. */
SET_BITVAL(sess->dataseq_inorder_en, options, BIT_9);