BIT_8
#define QLCNIC_FW_CAPABILITY_BDG BIT_8
cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
#define QLC_83XX_10_CAPABLE BIT_8
cmd.req.arg[1] = function | BIT_8;
if (*val & BIT_8)
if (status & BIT_8)
if (!(cmd->req.arg[1] & BIT_8))
cmd.req.arg[2] |= BIT_1 | BIT_3 | BIT_8;
#define ISP_FLASH_ENABLE BIT_8 /* Flash BIOS Read/Write enable */
#define TP_RENEGOTIATE BIT_8 /* Renegotiate on error. */
#define SF_GOT_BUS BIT_8 /* */
if (!(mpi_state & BIT_9 && mpi_state & BIT_8 && mpi_state & BIT_15)) {
#define FO1_SET_EMPHASIS_SWING BIT_8
#define MBX_8 BIT_8
#define PO_ENABLE_DIF_BUNDLING BIT_8
#define SS_RESPONSE_INFO_LEN_VALID BIT_8
#define NVME_PRLI_SP_SLER BIT_8
#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
#define RDP_PORT_SPEED_64GB BIT_8
#define FLOGI_SEQ_DEL BIT_8
#define DT_ISP2432 BIT_8
#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
#define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
#define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
#define CF_ADDITIONAL_PARAM_BLK BIT_8
#define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */
case BIT_8:
ha->fw_options[2] |= BIT_8;
ha->fw_options[2] &= ~BIT_8;
icb->firmware_options_3 |= cpu_to_le32(BIT_8);
icb->firmware_options_3 |= cpu_to_le32(BIT_8);
mb[1] & BIT_8 ? "" : " not",
if ((mb[1] & BIT_8) == 0)
rd_reg_word(®24->mailbox7) & BIT_8)
if (iop[0] & BIT_8)
if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
if (iop[0] & BIT_8)
#define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
pci_bus = (ha->pci_attr & BIT_8) >> 8;
nv->firmware_options_2 |= cpu_to_le32(BIT_8);
nv->firmware_options_2 &= ~cpu_to_le32(BIT_8);
nv->firmware_options_2 |= cpu_to_le32(BIT_8);
nv->firmware_options_2 &= ~cpu_to_le32(BIT_8);
#define CTIO7_FLAGS_DONT_RET_CTIO BIT_8
#define NOTIFY_ACK_RES_COUNT BIT_8
TRC_SRR_TERM = BIT_8,
#define OF_INC_RC BIT_8 /* Increment command resource count */
options |= BIT_8;
options &= ~BIT_8;
SET_BITVAL(sess->pdu_inorder_en, options, BIT_8);