BIT_6
#define QLC_83XX_FW_CAPABILITY_TSO BIT_6
arg1 |= (BIT_4 | BIT_6 | BIT_7);
arg1 &= ~BIT_6;
esw_cfg->promisc_mode = !!(arg1 & BIT_6);
if (adapter->ahw->capabilities & BIT_6) {
#define QLCNIC_DUMP_WRT_SAVED BIT_6
if (status & BIT_6)
cmd.req.arg[1] = ((func & 0xf) << 2) | BIT_6 | BIT_1;
cmd.req.arg[2] |= BIT_6;
mr |= BIT_6;
#define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
if (!(status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_4 |
status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_5 |
cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6);
status |= qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_2 |
qla1280_mailbox_command(ha, BIT_6 | BIT_3 | BIT_2 | BIT_1 | BIT_0,
return BIT_6;
return BIT_5 | BIT_6;
#define ISP_CFG1_F128 BIT_6 /* 128-byte FIFO threshold */
#define OF_DATA_IN BIT_6 /* Data in to initiator */
#define OF_NO_DATA (BIT_7 | BIT_6)
#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
#define MBX_6 BIT_6
#define CF_WRITE BIT_6
#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
#define SCM_EDC_ACC_RECEIVED BIT_6
#define FCF_FCSP_DEVICE BIT_6
#define SRB_WAKEUP_ON_COMP BIT_6
#define DT_ISP6322 BIT_6
#define FC_LL_S BIT_6 /* Short */
#define FC_TEC_SN BIT_6 /* short wave w/o OFC */
#define FC_MED_TP BIT_6 /* Twited Pair */
#define FC_SP_8 BIT_6
#define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
#define FO1_DISABLE_LED_CTRL BIT_6
#define PDF_ACK0_CAPABLE BIT_6
#define SF_NVME_ERSP BIT_6
#define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */
#define LCF_NVME_PRLI BIT_6 /* Perform NVME FC4 PRLI */
(BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
(BIT_7 | BIT_6 | BIT_5)) >> 5;
(BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
BIT_6) != 0;
nv->firmware_options[0] |= (BIT_6 | BIT_1);
nv->special_options[0] &= ~BIT_6;
if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
if ((icb->firmware_options[1] & BIT_6) == 0) {
(icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
(BIT_6 | BIT_5 | BIT_4)) >> 4;
(BIT_6 | BIT_5 | BIT_4)) >> 4;
if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
mcp->mb[1] |= BIT_6;
BIT_6)) {
mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
mcp->mb[1] = mreq->options | BIT_15 | BIT_6;
else if (subcode & (BIT_6 | BIT_7)) {
options |= BIT_6;
if (!(ha->fw_attributes & BIT_6))
if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6))
if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
sfp_flags |= BIT_6; /* sfp+ */
rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
tmp = ~(BIT_4|BIT_5|BIT_6);
tmp = ~(BIT_4|BIT_5|BIT_6);
#define CTIO7_FLAGS_STATUS_MODE_1 BIT_6
TRC_SRR_RSP = BIT_6,
#define OF_DATA_IN BIT_6 /* Data in to initiator */
#define OF_NO_DATA (BIT_7 | BIT_6)
chap_table->flags |= BIT_6; /* peer */
if (chap_table->flags & BIT_6)
SET_BITVAL(sess->auto_snd_tgt_disable, options, BIT_6);
SET_BITVAL(conn->snack_req_en, options, BIT_6);
SET_BITVAL(conn->tcp_timestamp_stat, options, BIT_6);
if (!(chap_table->flags & BIT_6)) /* Not BIDI */
if (chap_table->flags & BIT_6) /* peer */