BIT_3
#define QLCNIC_SWITCH_PROMISC_MODE BIT_3
#define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3
lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
#define QLC_83XX_SET_VXLAN_UDP_DPORT BIT_3
arg1 &= ~(BIT_2 | BIT_3);
arg2 |= (BIT_2 | BIT_3);
arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
arg2 &= ~BIT_3;
arg1 |= (BIT_3 | BIT_5);
if (mbx_out & BIT_3)
#define TA_CTL_BUSY BIT_3
#define QLCNIC_ENCAP_INNER_L4_UDP BIT_3
#define QLCNIC_DUMP_ORCRB BIT_3
if (status & BIT_3)
cmd.req.arg[2] |= BIT_1 | BIT_3 | BIT_8;
mr = BIT_3 | BIT_2 | BIT_1 | BIT_0;
#define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
BIT_3 | BIT_2 | BIT_1 | BIT_0,
BIT_3 | BIT_2 | BIT_1 | BIT_0,
BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
pkt->control_flags |= cpu_to_le16(BIT_3);
pkt->control_flags |= cpu_to_le16(BIT_3);
if (pkt->entry_status & BIT_3)
if (pkt->entry_status & (BIT_3 + BIT_2)) {
qla1280_mailbox_command(ha, BIT_6 | BIT_3 | BIT_2 | BIT_1 | BIT_0,
#define NV_DATA_IN BIT_3
#define CDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */
#define DDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */
#define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */
options |= BIT_3|BIT_2|BIT_1;
options |= BIT_3;
#define FO1_CTIO_RETRY BIT_3
#define MBX_3 BIT_3
#define GLSO_USE_DID BIT_3
#define CF_SIMPLE_TAG BIT_3
#define PO_ENABLE_INCR_GUARD_SEED BIT_3
#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
#define SS_BUSY_CONDITION BIT_3
#define IDC_HEARTBEAT_FAILURE BIT_3
#define NVME_PRLI_SP_DISCOVERY BIT_3
#define FCF_ASYNC_SENT BIT_3
#define DT_ISP2312 BIT_3
#define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
#define SRB_LOGIN_NVME_PRLI BIT_3
#define FC_LL_M BIT_3 /* Medium */
#define FC_TEC_ACT BIT_3 /* Active cable */
#define FC_MED_M6 BIT_3 /* Multimode, 62.5um */
#define FC_SP_32 BIT_3
#define SRB_FXDISC_RSP_DWRD_VALID BIT_3
#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
#define ISR_RISC_INT BIT_3 /* RISC interrupt */
#define NVR_DATA_IN BIT_3
#define AOF_ABTS_RTY_CNT BIT_3 /* Use driver specified retry count. */
#define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */
#define ISRX_RISC_INT BIT_3 /* RISC interrupt. */
#define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
#define GPDX_LED_GREEN_ON BIT_3
#define MDBS_NON_PARTIC BIT_3
#define FSTATE_LOGGED_IN BIT_3
#define VCO_DIAG_FW BIT_3
#define BD_WRAP_BACK BIT_3
#define CF_DIF_SEG_DESCR_ENABLE BIT_3
#define ECF_SEC_LOGIN BIT_3
#define TCF_ABORT_TASK_SET BIT_3
#define QLA2XX_CMD_TIMEOUT BIT_3
mb[1] = BIT_2 | BIT_3;
(BIT_4 | BIT_3)) >> 3;
(BIT_3 | BIT_2 | BIT_1 | BIT_0);
(BIT_3 | BIT_2 | BIT_1 | BIT_0);
ha->fw_options[2] |= BIT_3;
ha->fw_options[2] |= BIT_3;
nv->firmware_options[0] = BIT_3 | BIT_1;
nv->firmware_options[0] &= ~BIT_3;
ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
icb->firmware_options[0] &= ~BIT_3;
~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
(BIT_3 | BIT_2 | BIT_1 | BIT_0);
~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
(BIT_3 | BIT_2 | BIT_1 | BIT_0);
~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
(BIT_3 | BIT_2 | BIT_1 | BIT_0);
~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
RESOURCE_HA = BIT_3,
if (rd_reg_dword(®->iobase_c8) & BIT_3)
vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
} else if (subcode & (BIT_3 | BIT_4)) {
#define NVME_ENABLE_FLAG BIT_3
if ((pd->prli_svc_param_word_3[0] & BIT_3) == 0)
if (options & BIT_3) {
#define CF_DIF_SEG_DESCR_ENABLE BIT_3
#define NOTIFY_ACK_FLAGS_TERMINATE BIT_3
#define CTIO_CRC2_AF_DIF_DSD_ENA BIT_3
TRC_XFR_RDY = BIT_3,
#define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
conn->tcp_timer_scale |= BIT_3;
SET_BITVAL(sess->entry_state, options, BIT_3);
SET_BITVAL(sess->discovery_auth_optional, options, BIT_3);
SET_BITVAL(conn->tcp_timer_scale & BIT_2, options, BIT_3);
conn->tcp_timer_scale |= BIT_3;