BIT_2
#define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
#define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2
lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
val = BIT_2;
#define QLC_83XX_MATCH_ENCAP_ID BIT_2
arg1 &= ~(BIT_2 | BIT_3);
arg2 |= (BIT_2 | BIT_3);
arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
arg2 &= ~BIT_2;
if (!(esw_cfg->offload_flags & BIT_2))
arg1 |= (BIT_2 | BIT_5);
if (mbx_out & BIT_2)
#define TA_CTL_WRITE BIT_2
if (!(offload_flags & BIT_2))
#define QLCNIC_ENCAP_INNER_L3_IP6 BIT_2
esw_cfg.offload_flags |= (BIT_1 | BIT_2);
#define QLCNIC_DUMP_ANDCRB BIT_2
if (status & BIT_2)
mr = BIT_3 | BIT_2 | BIT_1 | BIT_0;
err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb);
#define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
#define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
BIT_3 | BIT_2 | BIT_1 | BIT_0,
BIT_3 | BIT_2 | BIT_1 | BIT_0,
BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
status |= qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_2 |
status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
else if (pkt->entry_status & BIT_2)
if (pkt->entry_status & (BIT_3 + BIT_2)) {
qla1280_mailbox_command(ha, BIT_6 | BIT_3 | BIT_2 | BIT_1 | BIT_0,
#define ISP_CFG1_BENAB BIT_2 /* Global Bus burst enable */
#define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */
#define RISC_INT BIT_2 /* RISC interrupt */
#define NV_DATA_OUT BIT_2
#define CDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
#define DDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
#define NV_START_BIT BIT_2
#define RF_BAD_HEADER BIT_2 /* Bad header. */
options |= BIT_3|BIT_2|BIT_1;
options |= BIT_2;
#define IOCTL_CMD BIT_2
#define IOCTL_CMD BIT_2
#define MBX_2 BIT_2
#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
#define NV_START_BIT BIT_2
#define CF_ORDERED_TAG BIT_2
#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
#define SS_CONDITION_MET BIT_2
#define IDC_NIC_FW_REPORTED_FAILURE BIT_2
#define FCF_FCP2_DEVICE BIT_2
#define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
#define DT_ISP2300 BIT_2
#define ENABLE_EXCHANGE_OFFLD BIT_2
#define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
#define SRB_LOGIN_SKIP_PRLI BIT_2
#define FC_LL_SA BIT_2 /* ShortWave laser */
#define FC_TEC_PAS BIT_2 /* Passive cable */
#define FC_MED_M5 BIT_2 /* Multimode, 50um */
#define FC_SP_2 BIT_2
#define SRB_FXDISC_REQ_DWRD_VALID BIT_2
#define NVR_DATA_OUT BIT_2
#define AOF_ABTS_TIMEOUT BIT_2 /* Disable logout on ABTS timeout. */
#define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
#define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
#define GPDX_LED_YELLOW_ON BIT_2
#define CS_VF_SET_HOPS_OF_VPORTS BIT_2
#define FSTATE_IS_DIAG_FW BIT_2
#define VCO_DONT_RESET_UPDATE BIT_2
#define CF_DATA_SEG_DESCR_ENABLE BIT_2
#define TMF_DSD_LIST_ENABLE BIT_2
#define TCF_CLEAR_TASK_SET BIT_2
#define QLA2XX_INT_ERR BIT_2
mb[1] = BIT_2 | BIT_3;
(ha->fw_attributes & BIT_2)) {
if (ha->fw_seriallink_options[3] & BIT_2) {
swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
(BIT_3 | BIT_2 | BIT_1 | BIT_0);
(BIT_3 | BIT_2 | BIT_1 | BIT_0);
nv->firmware_options[0] = BIT_2 | BIT_1;
nv->firmware_options[0] = BIT_2 | BIT_1;
nv->host_p[1] = BIT_2;
nv->firmware_options[0] |= BIT_2;
nv->firmware_options[0] |= BIT_2;
ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
icb->add_firmware_options[0] |= BIT_2;
(BIT_3 | BIT_2 | BIT_1 | BIT_0);
~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
(BIT_3 | BIT_2 | BIT_1 | BIT_0);
~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
(BIT_3 | BIT_2 | BIT_1 | BIT_0);
~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
RESOURCE_FORCE = BIT_2,
mcp->mb[2] = BIT_2;
if (subcode & BIT_2) {
if (!(subcode & (BIT_2 | BIT_5)))
if (options & BIT_2) {
(BIT_0 | BIT_1 | BIT_2);
#define CF_DATA_SEG_DESCR_ENABLE BIT_2
if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
#define QLA24XX_MGMT_LLD_OWNED BIT_2
#define CTIO7_FLAGS_DSD_PTR BIT_2
TRC_DO_WORK_ERR = BIT_2,
conn->tcp_timer_scale |= BIT_2;
SET_BITVAL(conn->tcp_timer_scale & BIT_2, options, BIT_3);
SET_BITVAL(conn->tcp_timer_scale & BIT_1, options, BIT_2);
conn->tcp_timer_scale |= BIT_2;