BIT_15
#define QLC_83XX_AUTONEG_ENABLE BIT_15
#define QLC_83XX_AUTONEG(data) ((data) & BIT_15)
#define QLCNIC_MBX_ASYNC_EVENT BIT_15
#define TP_DISCONNECT BIT_15 /* Disconnect privilege. */
#define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */
if (!(mpi_state & BIT_9 && mpi_state & BIT_8 && mpi_state & BIT_15)) {
#define MBX_15 BIT_15
#define PO_DIS_REF_TAG_VALD BIT_15
#define RDP_PORT_SPEED_1GB BIT_15
#define DT_ISP2031 BIT_15
#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
#define NVR_BUSY BIT_15
#define HSR_RISC_INT BIT_15 /* RISC interrupt */
#define CSRX_FUNCTION BIT_15 /* Function number. */
#define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
#define VCO_ENABLE_DSD BIT_15
#define FAC_OPT_FORCE_SEMAPHORE BIT_15
#define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13)
case BIT_15:
ha->fw_options[3] |= BIT_15;
ha->fw_options[3] &= ~BIT_15;
if (nv->host_p & cpu_to_le32(BIT_15)) {
if (nv->host_p & cpu_to_le32(BIT_15)) {
if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
ha->sf_init_cb->flags |= cpu_to_le16(BIT_15);
mcp->mb[2] = sw_em_1g | BIT_15;
mcp->mb[3] = sw_em_2g | BIT_15;
mcp->mb[4] = sw_em_4g | BIT_15;
mcp->mb[1] = mreq->options | BIT_15 | BIT_6;
0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
mcp->mb[10] = BIT_15;
#define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
nv->firmware_options_1 &= cpu_to_le32(~BIT_15);
nv->firmware_options_1 &= cpu_to_le32(~BIT_15);
#define CTIO7_FLAGS_SEND_STATUS BIT_15
TRC_CMD_DONE = BIT_15,
#define OF_SSTS BIT_15 /* Send SCSI status */