TEGRA_DIVIDER_ROUND_UP
if (sdmmc_mux->div_flags & TEGRA_DIVIDER_ROUND_UP)
clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \
TEGRA_DIVIDER_ROUND_UP, 0, 0, \
TEGRA_DIVIDER_ROUND_UP,\
29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
TEGRA_DIVIDER_ROUND_UP, 183, 0,
TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, NULL);
TEGRA_DIVIDER_ROUND_UP, 0, NULL);
TEGRA_DIVIDER_ROUND_UP, 0, NULL);
clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
TEGRA_DIVIDER_ROUND_UP,
TEGRA_DIVIDER_ROUND_UP,
TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
TEGRA_DIVIDER_ROUND_UP, _clk_num, \
clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
if (flags & TEGRA_DIVIDER_ROUND_UP)