TEGRA_DIVIDER_INT
30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
PLL_OUT(2, PLLP_OUTA, 24, TEGRA_DIVIDER_INT, 16, pll_p_out2_int),
30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
if (!(flags & TEGRA_DIVIDER_INT))
if (flags & TEGRA_DIVIDER_INT)