TEGRA30_CLK_GR3D2
{ TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
{ .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },
TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, 0, TEGRA30_CLK_GR3D2),