TEGRA30_CLK_DSIB
{ .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),