drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.c

2631

u16tmp |= BIT9;

drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h

101

#define ALGO_TRACE_SW_EXEC BIT9

drivers/scsi/lpfc/lpfc_hw4.h

782

#define LPFC_SLI4_INTR9 BIT9

drivers/staging/rtl8723bs/hal/odm.h

374

ODM_BB_RATE_ADAPTIVE = BIT9,

drivers/staging/rtl8723bs/hal/odm_DIG.c

22

PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 enable CCX */

drivers/staging/rtl8723bs/hal/odm_RegDefine11N.h

158

#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9

drivers/staging/rtl8723bs/include/rtl8723b_spec.h

205

#define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */

drivers/staging/rtl8723bs/include/rtl8723b_spec.h

234

#define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */

drivers/tty/synclink_gt.c

386

#define IRQ_RXIDLE BIT9 /* HDLC */

drivers/tty/synclink_gt.c

387

#define IRQ_RXBREAK BIT9 /* async */

drivers/tty/synclink_gt.c

4032

val |= BIT9;

drivers/tty/synclink_gt.c

4072

val |= BIT9;

drivers/tty/synclink_gt.c

4195

case HDLC_CRC_16_CCITT: val |= BIT9; break;

drivers/tty/synclink_gt.c

4196

case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;

drivers/tty/synclink_gt.c

4268

case HDLC_CRC_16_CCITT: val |= BIT9; break;

drivers/tty/synclink_gt.c

4269

case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;

drivers/tty/synclink_gt.c

4913

if (!(*(src+1) & (BIT9 + BIT8))) {