drivers/gpu/drm/bridge/ite-it6263.c

456

regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_COL_DEP, BIT8);

drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.h

100

#define ALGO_TRACE_SW_DETAIL BIT8

drivers/scsi/lpfc/lpfc_hw4.h

781

#define LPFC_SLI4_INTR8 BIT8

drivers/staging/rtl8723bs/hal/odm.h

373

ODM_BB_PWR_TRAIN = BIT8,

drivers/staging/rtl8723bs/hal/odm.h

399

ODM_RTL8723B = BIT8,

drivers/staging/rtl8723bs/hal/odm_DIG.c

22

PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 enable CCX */

drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c

132

RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8);

drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c

134

RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8);

drivers/staging/rtl8723bs/include/hal_com_reg.h

222

#define RRSR_24M BIT8

drivers/staging/rtl8723bs/include/hal_com_reg.h

284

#define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */

drivers/staging/rtl8723bs/include/rtl8723b_spec.h

206

#define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */

drivers/staging/rtl8723bs/include/rtl8723b_spec.h

235

#define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */

drivers/tty/synclink_gt.c

2284

if (gsr & (BIT8 << i))

drivers/tty/synclink_gt.c

388

#define IRQ_RXOVER BIT8

drivers/tty/synclink_gt.c

4034

val |= BIT8;

drivers/tty/synclink_gt.c

4074

val |= BIT8;

drivers/tty/synclink_gt.c

4123

if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&

drivers/tty/synclink_gt.c

4196

case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;

drivers/tty/synclink_gt.c

4269

case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;

drivers/tty/synclink_gt.c

4913

if (!(*(src+1) & (BIT9 + BIT8))) {