BIT7
#define BT_INFO_8192E_2ANT_B_FTP BIT7
#define BT_INFO_8723B_1ANT_B_FTP BIT7
#define BT_INFO_8723B_2ANT_B_FTP BIT7
#define BT_INFO_8821A_1ANT_B_FTP BIT7
#define BT_INFO_8821A_2ANT_B_FTP BIT7
#define ALGO_TRACE_SW BIT7
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
#define DATAOUT BIT7
#define LPFC_SLI4_INTR7 BIT7
#define BT_INFO_8723B_1ANT_B_FTP BIT7
#define BT_INFO_8723B_2ANT_B_FTP BIT7
((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */
((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */
((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */
ODM_BB_PWR_SAVE = BIT7,
PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); /* 0xc0c[7]= 1 max power among all RX ants */
u2tmp = RegRfMod_BW | BIT7;
#define HSISR_PDNINT BIT7
#define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet (Rx beacon, probe rsp) */
#define SDIO_HISR_TXBCNERR BIT7
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]= 0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF stable*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]= 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
#define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */
val |= BIT7;
val &= ~BIT7;
#define IRQ_DSR BIT7
val |= BIT7;
val |= BIT7;
val |= BIT7; /* 100, txclk = DPLL Input */
val = BIT7; break;
val = BIT7 + BIT6; break;
val |= BIT7 + BIT6 + BIT5; /* 1110 */
viafb_write_reg_mask(CR91, VIACR, 0, BIT7);
viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);
BIT5 + BIT6 + BIT7);
viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
BIT7 + BIT2 + BIT1 + BIT0);
viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7);
viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7);
viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7);
viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7);