BIT6
#define BT_INFO_8192E_2ANT_B_A2DP BIT6
real_byte5 &= ~BIT6;
#define BT_INFO_8723B_1ANT_B_A2DP BIT6
#define BT_INFO_8723B_2ANT_B_A2DP BIT6
real_byte5 &= ~BIT6;
#define BT_INFO_8821A_1ANT_B_A2DP BIT6
#define BT_INFO_8821A_2ANT_B_A2DP BIT6
#define ALGO_TRACE_FW_EXEC BIT6
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
#define DATAIN BIT6
#define EN_ATN_STOP BIT6
#define LPFC_SLI4_INTR6 BIT6
ctrl = BIT(15) | BIT6 | ((pparm->algorithm) << 2) | pparm->keyid;
ret = (dvobj->cam_cache[cam_id].ctrl & BIT6) ? true : false;
realByte5 &= ~BIT6;
#define BT_INFO_8723B_1ANT_B_A2DP BIT6
#define BT_INFO_8723B_2ANT_B_A2DP BIT6
((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */
((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */
((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */
ODM_BB_ANT_DIV = BIT6,
#define HSISR_RON_INT BIT6
#define RRSR_12M BIT6
#define RCR_CBSSID_DATA BIT6 /* Accept BSSID match packet (Data) */
#define SDIO_HISR_TXBCNOK BIT6
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */ \
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \
{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\
#define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */
#define DYNAMIC_BB_ANT_DIV BIT6 /* ODM_BB_ANT_DIV */
value |= BIT6;
value &= ~BIT6;
wr_reg32(info, RDCSR, BIT6);
#define IRQ_CTS BIT6
wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
val |= BIT6;
val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
val |= BIT6; /* 010, txclk = BRG */
val = BIT7 + BIT6; break;
default: val = BIT6; // NRZ encodings
tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
} else if (!(tcr & BIT6)) {
val |= BIT7 + BIT6 + BIT5; /* 1110 */
val |= BIT6; /* 0100 */
viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);
viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);
BIT5 + BIT6 + BIT7);
viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);