BIT5
#define BT_INFO_8192E_2ANT_B_HID BIT5
if ((byte1 & BIT4) && !(byte1 & BIT5)) {
real_byte1 |= BIT5;
real_byte5 |= BIT5;
#define BT_INFO_8723B_1ANT_B_HID BIT5
#define BT_INFO_8723B_2ANT_B_HID BIT5
if (byte1 & BIT4 && !(byte1 & BIT5)) {
real_byte1 |= BIT5;
real_byte5 |= BIT5;
#define BT_INFO_8821A_1ANT_B_HID BIT5
#define BT_INFO_8821A_2ANT_B_HID BIT5
#define ALGO_TRACE_FW_DETAIL BIT5
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
#define SRB_ERROR BIT5
#define RESIDUAL_VALID BIT5
#define EN_TAG_QUEUEING BIT5
#define LUN_CHECK BIT5
#define LPFC_SLI4_INTR5 BIT5
if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT5))
if (TEST_FLAG(pregistrypriv->stbc_cap, BIT5))
if (TEST_FLAG(pregistrypriv->beamform_cap, BIT5) && bHwSupportBeamformee)
realByte1 |= BIT5;
realByte5 |= BIT5;
if (byte1 & BIT4 && !(byte1 & BIT5)) {
#define BT_INFO_8723B_1ANT_B_HID BIT5
#define BT_INFO_8723B_2ANT_B_HID BIT5
rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT5)));
ODM_BB_CCK_PD = BIT5,
ODM_WM_AUTO = BIT5,
#define HSISR_SPS_OCP_INT BIT5
#define SDIO_HISR_RXFOVW BIT5
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TSF*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital , 1:isolation*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital , 1:isolation*/ \
#define BIT_BCN_PORT_SEL BIT5
#define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */
if (status & (BIT5 + BIT4)) {
if (status & (BIT5 + BIT4 + BIT3)) {
#define IRQ_DCD BIT5
case 7: val |= BIT5; break;
case 8: val |= BIT5 + BIT4; break;
case 7: val |= BIT5; break;
case 8: val |= BIT5 + BIT4; break;
case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
val |= BIT5; /* 001, txclk = RXC Input */
tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
tcr &= ~(BIT5 + BIT4);
val |= BIT5; /* 0010 */
val |= BIT7 + BIT6 + BIT5; /* 1110 */
info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
BIT5 + BIT6 + BIT7);
viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);
viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
(viafb_read_reg(VIASR, SR2A) & BIT5) >> 4 |
reg_val << 4, BIT5);