BIT3
if ((coex_sta->bt_info_ext & BIT3)) {
#define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT3
if (coex_sta->bt_info_ext & BIT3) {
#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
if ((coex_sta->bt_info_ext & BIT3)) {
#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3
if ((coex_sta->bt_info_ext & BIT3) && !wifi_under_5g) {
#define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT3
#define WIFI_P2P_GO_CONNECTED BIT3
#define ALGO_TRACE BIT3
#define WOW_UWF BIT3 /* Unicast Wakeup frame. */
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
#define UNDER_RUN BIT3
#define WIDE_NEGO_DONE BIT3
#define ACTIVE_NEGATION BIT3
#define UNIT_RETRY BIT3
#define LPFC_SLI4_INTR3 BIT3
if (pCoexSta->btInfoExt & BIT3) {
#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
if ((pCoexSta->btInfoExt & BIT3)) {
#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3
#define WIFI_P2P_GO_CONNECTED BIT3
((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */
if ((cond1 & BIT3) != 0) /* APA */
((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */
if ((cond1 & BIT3) != 0) /* APA */
((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */
if ((cond1 & BIT3) != 0) /* APA */
rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT3)));
ODM_BB_FA_CNT = BIT3,
ODM_WM_N24G = BIT3,
pDM_PSTable->RegC70 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0xc70, bMaskDWord)&BIT3)>>3;
PHY_SetBBReg(pDM_Odm->Adapter, 0xc70, BIT3, 0); /* RegC70[3]= 1'b0 */
PHY_SetBBReg(pDM_Odm->Adapter, 0xc70, BIT3, pDM_PSTable->RegC70);
if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
#define RRSR_11M BIT3
#define RCR_AB BIT3 /* Accept broadcast packet */
#define SDIO_HISR_RXERR BIT3
RTW_GSPI = BIT3,
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]= 0 and WLSUS_EN 0x04[11]= 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define IMR_VIDOK_8723B BIT3 /* AC_VI DMA OK */
#define LDPC_HT_CAP_TX BIT3
#define STBC_HT_CAP_TX BIT3
if (status & BIT3) {
if (status & (BIT5 + BIT4 + BIT3)) {
wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
val |= BIT3;
val |= BIT3;
val |= BIT3; /* 010, rxclk = BRG */
if (status & BIT3)
val |= BIT3;
val |= BIT3;
val &= ~BIT3;
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2 + BIT3);
viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
BIT0 + BIT1 + BIT2 + BIT3);
viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);