BIT2
#define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT2
#define WIFI_HS_CONNECTED BIT2
#define INTF_NOTIFY BIT2
#define ALGO_BT_MONITOR BIT2
#define WOW_MAGIC BIT2 /* Magic packet */
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
#define RESET_DONE BIT2
#define OVER_RUN BIT2
#define RESET_DEV0 BIT2
#define WIDE_NEGO_ENABLE BIT2
#define RST_SCSI_BUS BIT2
#define FORMATING_MEDIA BIT2
#define ASPI_SUPPORT BIT2
#define LPFC_SLI4_INTR2 BIT2
#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
#define WIFI_HS_CONNECTED BIT2
((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */
if ((cond1 & BIT2) != 0) /* ALNA */
((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */
if ((cond1 & BIT2) != 0) /* ALNA */
((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */
if ((cond1 & BIT2) != 0) /* ALNA */
ODM_BB_DYNAMIC_TXPWR = BIT2,
while (val & BIT2) {
rtw_write8(padapter, REG_SYS_FUNC_EN + 1, val & (~BIT2));
#define DF_IO_BIT BIT2
#define RRSR_5_5M BIT2
#define BW_OPMODE_20MHZ BIT2
#define RCR_AM BIT2 /* Accept multicast packet */
#define SDIO_HISR_TXERR BIT2
#define WL_FUNC_EN BIT2 /* WiFi function enable */
RTW_SDIO = BIT2,
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/ \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]= 0 and WLSUS_EN 0x04[11]= 0*/ \
#define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */
RTW_ROAM_ACTIVE = BIT2,
#define DYNAMIC_BB_DYNAMIC_TXPWR BIT2 /* ODM_BB_DYNAMIC_TXPWR */
#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
if (status & BIT2) {
wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
wr_reg32(info, RDCSR, (BIT2 + BIT0));
wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
(unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
wr_reg32(info, TDCSR, BIT2 + BIT0);
wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
val = BIT2;
val |= BIT2; /* 001, rxclk = TXC Input */
if (status & BIT2)
val |= BIT2;
val |= BIT2;
val &= ~BIT2;
BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2 + BIT3);
p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2);
BIT7 + BIT2 + BIT1 + BIT0);
(viafb_read_reg(VIASR, SR1E) & BIT2) >> 2;
reg_val << 2, BIT2);