drivers/scsi/lpfc/lpfc_hw4.h

785

#define LPFC_SLI4_INTR12 BIT12

drivers/staging/rtl8723bs/hal/odm.h

377

ODM_BB_RXHP = BIT12,

drivers/staging/rtl8723bs/hal/odm_DIG.c

664

PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1);

drivers/staging/rtl8723bs/include/rtl8723b_spec.h

203

#define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */

drivers/tty/synclink_gt.c

383

#define IRQ_TXIDLE BIT12

drivers/tty/synclink_gt.c

4187

case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;

drivers/tty/synclink_gt.c

4188

case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;

drivers/tty/synclink_gt.c

4189

case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;

drivers/tty/synclink_gt.c

4190

case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;

drivers/tty/synclink_gt.c

4260

case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;

drivers/tty/synclink_gt.c

4261

case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;

drivers/tty/synclink_gt.c

4262

case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;

drivers/tty/synclink_gt.c

4263

case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;