drivers/scsi/lpfc/lpfc_hw4.h

784

#define LPFC_SLI4_INTR11 BIT11

drivers/staging/rtl8723bs/core/rtw_efuse.c

116

rtw_write16(padapter, 0x34, rtw_read16(padapter, 0x34) & (~BIT11));

drivers/staging/rtl8723bs/hal/odm.h

376

ODM_BB_PSD = BIT11,

drivers/staging/rtl8723bs/hal/odm_DIG.c

212

PHY_SetBBReg(pDM_Odm->Adapter, REG_RD_CTRL, BIT11, 1); /* stop counting if EDCCA is asserted */

drivers/staging/rtl8723bs/hal/odm_RegDefine11N.h

160

#define ODM_BIT_BB_ATC_11N BIT11

drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c

65

pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11);

drivers/staging/rtl8723bs/include/hal_com_reg.h

283

#define RCR_ADF BIT11 /* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */

drivers/staging/rtl8723bs/include/rtl8723b_spec.h

232

#define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */

drivers/tty/synclink_gt.c

384

#define IRQ_TXUNDER BIT11 /* HDLC */

drivers/tty/synclink_gt.c

4185

case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;

drivers/tty/synclink_gt.c

4186

case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;

drivers/tty/synclink_gt.c

4189

case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;

drivers/tty/synclink_gt.c

4190

case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;

drivers/tty/synclink_gt.c

4258

case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;

drivers/tty/synclink_gt.c

4259

case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;

drivers/tty/synclink_gt.c

4262

case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;

drivers/tty/synclink_gt.c

4263

case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;