drivers/scsi/lpfc/lpfc_hw4.h

783

#define LPFC_SLI4_INTR10 BIT10

drivers/staging/rtl8723bs/hal/odm.h

375

ODM_BB_PATH_DIV = BIT10,

drivers/staging/rtl8723bs/hal/odm_DIG.c

22

PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); /* 0x890[9:8]=3 enable CCX */

drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c

65

pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11);

drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c

71

pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10);

drivers/staging/rtl8723bs/include/rtl8723b_spec.h

204

#define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */

drivers/staging/rtl8723bs/include/rtl8723b_spec.h

233

#define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */

drivers/tty/synclink_gt.c

2043

if (count == info->rbuf_fill_level || (reg & BIT10)) {

drivers/tty/synclink_gt.c

385

#define IRQ_RXDATA BIT10

drivers/tty/synclink_gt.c

4184

case HDLC_ENCODING_NRZB: val |= BIT10; break;

drivers/tty/synclink_gt.c

4186

case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;

drivers/tty/synclink_gt.c

4188

case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;

drivers/tty/synclink_gt.c

4190

case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;

drivers/tty/synclink_gt.c

4257

case HDLC_ENCODING_NRZB: val |= BIT10; break;

drivers/tty/synclink_gt.c

4259

case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;

drivers/tty/synclink_gt.c

4261

case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;

drivers/tty/synclink_gt.c

4263

case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;