BIT1
if ((coex_sta->bt_info_ext & BIT1)) {
#define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT0 | BIT1);
if (coex_sta->bt_info_ext & BIT1) {
#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT0 | BIT1);
if ((coex_sta->bt_info_ext & BIT1)) {
#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
if (coex_sta->bt_info_ext & BIT1) {
#define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT1
if ((coex_sta->bt_info_ext & BIT1)) {
#define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1
#define WIFI_AP_CONNECTED BIT1
#define ALGO_WIFI_RSSI_STATE BIT1
#define WOW_WOMEN BIT1 /* WoW function on or off. */
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
#define RESET_DETECT BIT1
#define ABORTION BIT1
#define ABORT_DEV BIT1
#define SYNC_NEGO_DONE BIT1
#define GREATER_1G BIT1
#define UNIT_INFO_CHANGED BIT1
#define SCSI_SUPPORT BIT1
#define LPFC_SLI4_INTR1 BIT1
phtpriv->sgi_40m = TEST_FLAG(pregistrypriv->short_gi, BIT1) ? true : false;
pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp | BIT0 | BIT1);
if (pCoexSta->btInfoExt & BIT1) {
#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp | BIT0 | BIT1);
if ((pCoexSta->btInfoExt & BIT1)) {
#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
#define WIFI_AP_CONNECTED BIT1
if ((cond1 & BIT1) != 0) /* GPA */
if ((cond1 & BIT1) != 0) /* GPA */
if ((cond1 & BIT1) != 0) /* GPA */
ODM_BB_RA_MASK = BIT1,
ODM_WM_G = BIT1,
PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);
PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);
ODM_RESUME_DIG = BIT1
rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1);
rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1);
rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
#define DF_RX_BIT BIT1
#define RRSR_2M BIT1
#define RCR_APM BIT1 /* Accept physical match packet */
#define SDIO_HIMR_AVAL_MSK BIT1
#define SDIO_HISR_AVAL BIT1
#define WL_HWPDN_SL BIT1 /* WiFi HW PDn polarity control */
RTW_USB = BIT1,
#define ANT_DETECT_BY_RSSI BIT1
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*disable security engine*/ \
{0x0286, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA idle */ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1, enable security engine*/\
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
#define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */
RTW_CMDF_WAIT_ACK = BIT1,
#define LDPC_HT_ENABLE_TX BIT1
#define STBC_HT_ENABLE_TX BIT1
#define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */
RTW_ROAM_ON_RESUME = BIT1,
#define RT_PCI_ASPM_OSC_DISABLE BIT1 /* PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM */
status = *(p + 1) & (BIT1 + BIT0);
if (status & BIT1)
if (status & BIT1)
#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
if (status & BIT1) {
#define MASK_PARITY BIT1
wr_reg32(info, RDCSR, BIT1);
wr_reg32(info, TDCSR, BIT1);
val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
(unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
val |= BIT1 + BIT0;
if (status & BIT1)
val |= BIT1;
status &= ~BIT1;
} else if (status & BIT1) {
*p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
(unsigned short)(rd_reg16(info, TCR) | BIT1));
viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2 + BIT3);
viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2 + BIT3);
viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
BIT0 + BIT1 + BIT2 + BIT3);
BIT0 + BIT1 + BIT2);
viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
BIT7 + BIT2 + BIT1 + BIT0);
viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1);
(viafb_read_reg(VIASR, SR1B) & BIT1) >> 1;
reg_val << 1, BIT1);