TB_CFG_SWITCH
ret = tb_sw_read(sw, &header, TB_CFG_SWITCH, offset, 2);
ret = tb_sw_read(sw, &header, TB_CFG_SWITCH, offset, 1);
ret = tb_sw_read(sw, &header, TB_CFG_SWITCH, offset, 1);
ret = tb_sw_read(sw, &value, TB_CFG_SWITCH, offset, 1);
return tb_sw_write(sw, &value, TB_CFG_SWITCH, offset, 1);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
return tb_sw_write(sw, &val, TB_CFG_SWITCH,
TB_CFG_SWITCH, 0, 1,
ret = tb_sw_read(sw, &data, TB_CFG_SWITCH, cap + offset + i, 1);
ret = tb_sw_read(sw, data, TB_CFG_SWITCH, cap + offset, dwords);
ret = tb_sw_read(sw, &header, TB_CFG_SWITCH, cap, 1);
ret = tb_sw_read(sw, (u32 *)&header + 1, TB_CFG_SWITCH,
ret = tb_sw_read(sw, data, TB_CFG_SWITCH, 0, dwords);
ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, offset, 1);
return regs_write(sw, NULL, TB_CFG_SWITCH, user_buf, count, ppos);
res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + ROUTER_CS_4, 1);
return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + ROUTER_CS_4, 1);
return pcie2cio_write(tb_priv(tb), TB_CFG_SWITCH, 0, 0x777, BIT(1));
return pcie2cio_write(tb_priv(tb), TB_CFG_SWITCH, 0, 0x50, BIT(9));
res = tb_cfg_read_raw(tb->ctl, &tmp, 0, 0, TB_CFG_SWITCH,
ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4);
ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_LINK_ATTR, 1);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_CS_42, 1);
return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_LINK_REQ, 1);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_LINK_REQ, 1);
return tb_sw_write(sw, &val, TB_CFG_SWITCH, cap + TB_LC_LINK_REQ, 1);
ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH,
return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, offset + TB_LC_SX_CTRL, 1);
ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH,
ret = tb_sw_write(sw, &ctrl, TB_CFG_SWITCH,
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_PORT_ATTR, 1);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
return tb_sw_write(sw, &in, TB_CFG_SWITCH, TB_LC_POWER, 1);
ret = tb_sw_read(sw, &mode, TB_CFG_SWITCH, cap + TB_LC_PORT_MODE, 1);
ret = tb_sw_write(sw, &mode, TB_CFG_SWITCH, cap + TB_LC_PORT_MODE, 1);
ret = tb_sw_read(sw, &mode, TB_CFG_SWITCH, cap + TB_LC_PORT_MODE, 1);
return tb_sw_write(sw, &mode, TB_CFG_SWITCH, cap + TB_LC_PORT_MODE, 1);
TB_CFG_SWITCH, 2, 2);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_3, 1);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1);
res = tb_sw_read(sw, &data, TB_CFG_SWITCH, sw->cap_plug_events + 1, 1);
return tb_sw_write(sw, &data, TB_CFG_SWITCH,
ret = tb_cfg_read(tb->ctl, &sw->config, route, 0, TB_CFG_SWITCH, 0, 5);
ret = tb_sw_write(sw, (u32 *)&sw->config + 1, TB_CFG_SWITCH,
ret = tb_sw_write(sw, (u32 *)&sw->config + 1, TB_CFG_SWITCH,
ret = tb_sw_write(sw, &value, TB_CFG_SWITCH, offset, 1);
ret = tb_sw_write(sw, &command, TB_CFG_SWITCH, offset, 1);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
return tb_sw_write(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1);
return tb_sw_write(sw, &val, TB_CFG_SWITCH, offset, 1);
ret = tb_sw_read(root_switch, gm_local_time, TB_CFG_SWITCH,
ret = tb_sw_write(sw, &local_time, TB_CFG_SWITCH,
ret = tb_sw_write(sw, &post_time, TB_CFG_SWITCH, post_time_offset, 2);
ret = tb_sw_write(sw, &post_time_high, TB_CFG_SWITCH,
ret = tb_sw_read(sw, &post_time, TB_CFG_SWITCH,
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
ret = tb_sw_read(sw, rx_data, TB_CFG_SWITCH, ROUTER_CS_9,
if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1))
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
ret = tb_sw_write(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
ret = tb_sw_write(sw, tx_data, TB_CFG_SWITCH, ROUTER_CS_9,
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
ret = tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);