TEGRA210_MBDRC_CFG
{ TEGRA210_MBDRC_CFG, 0x0030de51},
SOC_ENUM_SINGLE(TEGRA210_MBDRC_CFG, TEGRA210_MBDRC_CFG_MBDRC_MODE_SHIFT,
SOC_ENUM_SINGLE(TEGRA210_MBDRC_CFG, TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT,
SOC_ENUM_SINGLE(TEGRA210_MBDRC_CFG,
SOC_ENUM_SINGLE(TEGRA210_MBDRC_CFG, TEGRA210_MBDRC_CFG_FRAME_SIZE_SHIFT,
SOC_SINGLE_EXT("MBDRC RMS Offset", TEGRA210_MBDRC_CFG,
SOC_SINGLE_EXT("MBDRC Shift Control", TEGRA210_MBDRC_CFG,
case TEGRA210_MBDRC_CFG ... TEGRA210_MBDRC_CFG_RAM_DATA:
regmap_read(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, &val);
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG,
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG,
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG,
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG,
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG,
regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG,