drivers/net/ethernet/mscc/ocelot.h

82

*target = reg >> TARGET_OFFSET;

drivers/net/ethernet/mscc/ocelot_io.c

129

target = regfields[i].reg >> TARGET_OFFSET;

drivers/net/ethernet/mscc/ocelot_io.c

69

u16 target = reg >> TARGET_OFFSET;

drivers/net/ethernet/mscc/ocelot_io.c

82

u16 target = reg >> TARGET_OFFSET;

include/soc/mscc/ocelot.h

104

#define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)

include/soc/mscc/ocelot.h

128

ANA_ADVLEARN = ANA << TARGET_OFFSET,

include/soc/mscc/ocelot.h

227

QS_XTR_GRP_CFG = QS << TARGET_OFFSET,

include/soc/mscc/ocelot.h

239

QSYS_PORT_MODE = QSYS << TARGET_OFFSET,

include/soc/mscc/ocelot.h

310

REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,

include/soc/mscc/ocelot.h

323

SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,

include/soc/mscc/ocelot.h

489

PTP_PIN_CFG = PTP << TARGET_OFFSET,

include/soc/mscc/ocelot.h

498

GCB_SOFT_RST = GCB << TARGET_OFFSET,

include/soc/mscc/ocelot.h

502

DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET,