SZ_256
.end = OMAP1510_MCBSP2_BASE + SZ_256,
.end = OMAP1510_MCBSP3_BASE + SZ_256,
.end = OMAP1610_MCBSP1_BASE + SZ_256,
.end = OMAP1610_MCBSP2_BASE + SZ_256,
.end = OMAP1610_MCBSP3_BASE + SZ_256,
.end = OMAP1510_MCBSP1_BASE + SZ_256,
scu_base = ioremap(scu_a9_get_base(), SZ_256);
[0] = DEFINE_RES_MEM(S3C64XX_PA_IIS0, SZ_256),
[0] = DEFINE_RES_MEM(S3C64XX_PA_IIS1, SZ_256),
[0] = DEFINE_RES_MEM(S3C_PA_UART0, SZ_256),
[0] = DEFINE_RES_MEM(S3C_PA_UART1, SZ_256),
[0] = DEFINE_RES_MEM(S3C_PA_UART2, SZ_256),
[0] = DEFINE_RES_MEM(S3C_PA_UART3, SZ_256),
[0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
[0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
#define TEGRA_UARTC_SIZE SZ_256
#define TEGRA_UARTD_SIZE SZ_256
#define TEGRA_UARTE_SIZE SZ_256
#define TEGRA_PMC_SIZE SZ_256
.length = SZ_256,
.end = 0xA4000000 + SZ_256 - 1,
.end = 0xA4000000 + SZ_256 - 1,
.end = 0x07ffff00 + SZ_256 - 1,
pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1,
pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0);
#define GAUDI2_DMA_POOL_BLK_SIZE SZ_256 /* 256 bytes */
#define FW_VERSION_STR_SIZE SZ_256
#define QAIC_DBC_Q_GAP SZ_256
gran = SZ_256;
#define DMA_CHAN_BOFF_MAX (SZ_256 - 1)
const size_t pathlen = SZ_256;
const size_t namesize = SZ_256;
const size_t namesize = SZ_256;
ret = drm_mode_size_dumb(dev, args, SZ_256, 0);
KUNIT_EXPECT_EQ(test, GUC_NUM_DOORBELLS, SZ_256);
hweight64(gt->info.engine_mask) : SZ_256;
else if (IS_ALIGNED(len, SZ_256))
pitch = SZ_256;
#define PAGE_COPY_MODE_PS SZ_256 /* hw uses 256 bytes as the page-size */
#define ITS_ITT_ALIGN SZ_256
unsigned int pcm_size = SZ_256;
unsigned int partition_table = SZ_256;
#define FRAMEID_ALIGN SZ_256
case SZ_256:
io_sq->tx_max_header_size = min_t(u32, ena_dev->tx_max_header_size, SZ_256);
spc_size = pxpcs->reg_width * SZ_256;
.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_256, },
resource_set_range(r, 0, SZ_256);
#define DEFAULT_CARDBUS_IO_SIZE SZ_256
#define PORTWELL_EC_IOSPACE_LEN SZ_256
#define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256)
.txfifo = SZ_256,
#define MTK_SPI_IPM_PACKET_LOOP SZ_256
sf = tbstream_dev_alloc_tx(sdev, TBSTREAM_CLOSE, NULL, SZ_256);
r2.size = SZ_256;
phys_addr_t gap_size = SZ_256;
allocated_ptr = run_memblock_alloc(SZ_256, SMP_CACHE_BYTES);
phys_addr_t available_size = SZ_256;
phys_addr_t available_size = SZ_256;
r2.size = SZ_256;
min_addr = req_node_end - SZ_256;
min_addr = node2->base - SZ_256;
min_addr = req_node_end - SZ_256;
min_addr = node2->base - SZ_256;
min_addr = req_node->base - SZ_256;
phys_addr_t size = SZ_256;
phys_addr_t size = SZ_256;
max_addr = memblock_end_of_DRAM() + SZ_256;
max_addr = memblock_end_of_DRAM() - SZ_256;
min_addr = req_node_end - SZ_256;
min_addr = exp_node_end - SZ_256;
min_addr = node2->base - SZ_256;
min_addr = req_node_end - SZ_256;
min_addr = req_node->base - SZ_256;
min_addr = node2->base - SZ_256;
phys_addr_t size = SZ_256;
phys_addr_t size = SZ_256;
phys_addr_t r3_size = SZ_256;
phys_addr_t r3_size = SZ_256;
phys_addr_t size = SZ_256;
max_addr = memblock_end_of_DRAM() + SZ_256;
min_addr = memblock_start_of_DRAM() - SZ_256;
phys_addr_t size = SZ_256;
phys_addr_t r3_size = SZ_256;