drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h

35

#define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h

41

#define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h

45

#define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h

53

#define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h

63

#define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h

76

#define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h

79

#define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c

35

#define BYPASSCTRL_SYS (SYS_GPCPLL_CFG_BASE + 0x340)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c

50

#define GPCPLL_DVFS0 (SYS_GPCPLL_CFG_BASE + 0x10)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c

60

#define GPCPLL_DVFS1 (SYS_GPCPLL_CFG_BASE + 0x14)