arch/arm64/kvm/hyp/nvhe/sys_regs.c

372

#define AARCH32(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch32 }

arch/arm64/kvm/hyp/nvhe/sys_regs.c

375

#define AARCH64(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch64 }

arch/arm64/kvm/hyp/nvhe/sys_regs.c

388

#define RAZ_WI(REG) { SYS_DESC(REG), .access = pvm_access_raz_wi }

arch/arm64/kvm/hyp/nvhe/sys_regs.c

391

#define HOST_HANDLED(REG) { SYS_DESC(REG), .access = NULL }

arch/arm64/kvm/hyp/nvhe/sys_regs.c

505

{ SYS_DESC(SYS_ICC_SRE_EL1), .access = pvm_gic_read_sre, },

arch/arm64/kvm/hyp/nvhe/sys_regs.c

509

{ SYS_DESC(SYS_CCSIDR2_EL1), .access = pvm_idst_access },

arch/arm64/kvm/hyp/nvhe/sys_regs.c

510

{ SYS_DESC(SYS_GMID_EL1), .access = pvm_idst_access },

arch/arm64/kvm/hyp/nvhe/sys_regs.c

511

{ SYS_DESC(SYS_SMIDR_EL1), .access = pvm_idst_access },

arch/arm64/kvm/sys_regs.c

1475

{ SYS_DESC(SYS_DBGBVRn_EL1(n)), \

arch/arm64/kvm/sys_regs.c

1478

{ SYS_DESC(SYS_DBGBCRn_EL1(n)), \

arch/arm64/kvm/sys_regs.c

1481

{ SYS_DESC(SYS_DBGWVRn_EL1(n)), \

arch/arm64/kvm/sys_regs.c

1484

{ SYS_DESC(SYS_DBGWCRn_EL1(n)), \

arch/arm64/kvm/sys_regs.c

1489

SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \

arch/arm64/kvm/sys_regs.c

1506

#define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }

arch/arm64/kvm/sys_regs.c

1507

#define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }

arch/arm64/kvm/sys_regs.c

1508

#define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }

arch/arm64/kvm/sys_regs.c

1509

#define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }

arch/arm64/kvm/sys_regs.c

1524

{ SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \

arch/arm64/kvm/sys_regs.c

2613

SYS_DESC(SYS_##name), \

arch/arm64/kvm/sys_regs.c

2656

SYS_DESC(SYS_##name), \

arch/arm64/kvm/sys_regs.c

2702

SYS_DESC(SYS_##name), \

arch/arm64/kvm/sys_regs.c

3170

SYS_DESC(SYS_##reg), \

arch/arm64/kvm/sys_regs.c

3198

{ SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },

arch/arm64/kvm/sys_regs.c

3199

{ SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },

arch/arm64/kvm/sys_regs.c

3215

{ SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

3216

{ SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 },

arch/arm64/kvm/sys_regs.c

3217

{ SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,

arch/arm64/kvm/sys_regs.c

3219

{ SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

3220

{ SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

3221

{ SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

3222

{ SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

3223

{ SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },

arch/arm64/kvm/sys_regs.c

3225

{ SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

3226

{ SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

3228

{ SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

3230

{ SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 },

arch/arm64/kvm/sys_regs.c

3233

{ SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },

arch/arm64/kvm/sys_regs.c

3245

{ SYS_DESC(SYS_ID_DFR0_EL1),

arch/arm64/kvm/sys_regs.c

3377

{ SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },

arch/arm64/kvm/sys_regs.c

3378

{ SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },

arch/arm64/kvm/sys_regs.c

3379

{ SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },

arch/arm64/kvm/sys_regs.c

3380

{ SYS_DESC(SYS_SCTLR2_EL1), access_vm_reg, reset_val, SCTLR2_EL1, 0,

arch/arm64/kvm/sys_regs.c

3386

{ SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },

arch/arm64/kvm/sys_regs.c

3387

{ SYS_DESC(SYS_TRFCR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3388

{ SYS_DESC(SYS_SMPRI_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3389

{ SYS_DESC(SYS_SMCR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3390

{ SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },

arch/arm64/kvm/sys_regs.c

3391

{ SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },

arch/arm64/kvm/sys_regs.c

3392

{ SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },

arch/arm64/kvm/sys_regs.c

3393

{ SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0,

arch/arm64/kvm/sys_regs.c

3402

{ SYS_DESC(SYS_SPSR_EL1), access_spsr},

arch/arm64/kvm/sys_regs.c

3403

{ SYS_DESC(SYS_ELR_EL1), access_elr},

arch/arm64/kvm/sys_regs.c

3405

{ SYS_DESC(SYS_ICC_PMR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3407

{ SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },

arch/arm64/kvm/sys_regs.c

3408

{ SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },

arch/arm64/kvm/sys_regs.c

3409

{ SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },

arch/arm64/kvm/sys_regs.c

3411

{ SYS_DESC(SYS_ERRIDR_EL1), access_ras },

arch/arm64/kvm/sys_regs.c

3412

{ SYS_DESC(SYS_ERRSELR_EL1), access_ras },

arch/arm64/kvm/sys_regs.c

3413

{ SYS_DESC(SYS_ERXFR_EL1), access_ras },

arch/arm64/kvm/sys_regs.c

3414

{ SYS_DESC(SYS_ERXCTLR_EL1), access_ras },

arch/arm64/kvm/sys_regs.c

3415

{ SYS_DESC(SYS_ERXSTATUS_EL1), access_ras },

arch/arm64/kvm/sys_regs.c

3416

{ SYS_DESC(SYS_ERXADDR_EL1), access_ras },

arch/arm64/kvm/sys_regs.c

3417

{ SYS_DESC(SYS_ERXPFGF_EL1), access_ras },

arch/arm64/kvm/sys_regs.c

3418

{ SYS_DESC(SYS_ERXPFGCTL_EL1), access_ras },

arch/arm64/kvm/sys_regs.c

3419

{ SYS_DESC(SYS_ERXPFGCDN_EL1), access_ras },

arch/arm64/kvm/sys_regs.c

3420

{ SYS_DESC(SYS_ERXMISC0_EL1), access_ras },

arch/arm64/kvm/sys_regs.c

3421

{ SYS_DESC(SYS_ERXMISC1_EL1), access_ras },

arch/arm64/kvm/sys_regs.c

3422

{ SYS_DESC(SYS_ERXMISC2_EL1), access_ras },

arch/arm64/kvm/sys_regs.c

3423

{ SYS_DESC(SYS_ERXMISC3_EL1), access_ras },

arch/arm64/kvm/sys_regs.c

3428

{ SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },

arch/arm64/kvm/sys_regs.c

3429

{ SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },

arch/arm64/kvm/sys_regs.c

3431

{ SYS_DESC(SYS_PMSCR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3432

{ SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3433

{ SYS_DESC(SYS_PMSICR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3434

{ SYS_DESC(SYS_PMSIRR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3435

{ SYS_DESC(SYS_PMSFCR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3436

{ SYS_DESC(SYS_PMSEVFR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3437

{ SYS_DESC(SYS_PMSLATFR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3438

{ SYS_DESC(SYS_PMSIDR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3439

{ SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3440

{ SYS_DESC(SYS_PMBPTR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3441

{ SYS_DESC(SYS_PMBSR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3442

{ SYS_DESC(SYS_PMSDSFR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3451

{ SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },

arch/arm64/kvm/sys_regs.c

3453

{ SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },

arch/arm64/kvm/sys_regs.c

3454

{ SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1,

arch/arm64/kvm/sys_regs.c

3456

{ SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1,

arch/arm64/kvm/sys_regs.c

3458

{ SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1,

arch/arm64/kvm/sys_regs.c

3460

{ SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },

arch/arm64/kvm/sys_regs.c

3462

{ SYS_DESC(SYS_LORSA_EL1), trap_loregion },

arch/arm64/kvm/sys_regs.c

3463

{ SYS_DESC(SYS_LOREA_EL1), trap_loregion },

arch/arm64/kvm/sys_regs.c

3464

{ SYS_DESC(SYS_LORN_EL1), trap_loregion },

arch/arm64/kvm/sys_regs.c

3465

{ SYS_DESC(SYS_LORC_EL1), trap_loregion },

arch/arm64/kvm/sys_regs.c

3466

{ SYS_DESC(SYS_MPAMIDR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3467

{ SYS_DESC(SYS_LORID_EL1), trap_loregion },

arch/arm64/kvm/sys_regs.c

3469

{ SYS_DESC(SYS_MPAM1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3470

{ SYS_DESC(SYS_MPAM0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3471

{ SYS_DESC(SYS_MPAMSM_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3473

{ SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },

arch/arm64/kvm/sys_regs.c

3474

{ SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },

arch/arm64/kvm/sys_regs.c

3476

{ SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3477

{ SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3478

{ SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3479

{ SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3480

{ SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3481

{ SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3482

{ SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3483

{ SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3484

{ SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3485

{ SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3486

{ SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3487

{ SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3488

{ SYS_DESC(SYS_ICC_IDR0_EL1), access_gicv5_idr0 },

arch/arm64/kvm/sys_regs.c

3489

{ SYS_DESC(SYS_ICC_IAFFIDR_EL1), access_gicv5_iaffid },

arch/arm64/kvm/sys_regs.c

3490

{ SYS_DESC(SYS_ICC_PPI_ENABLER0_EL1), access_gicv5_ppi_enabler },

arch/arm64/kvm/sys_regs.c

3491

{ SYS_DESC(SYS_ICC_PPI_ENABLER1_EL1), access_gicv5_ppi_enabler },

arch/arm64/kvm/sys_regs.c

3492

{ SYS_DESC(SYS_ICC_DIR_EL1), access_gic_dir },

arch/arm64/kvm/sys_regs.c

3493

{ SYS_DESC(SYS_ICC_RPR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3494

{ SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },

arch/arm64/kvm/sys_regs.c

3495

{ SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },

arch/arm64/kvm/sys_regs.c

3496

{ SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },

arch/arm64/kvm/sys_regs.c

3497

{ SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3498

{ SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3499

{ SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3500

{ SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3501

{ SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3502

{ SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },

arch/arm64/kvm/sys_regs.c

3503

{ SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3504

{ SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3506

{ SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },

arch/arm64/kvm/sys_regs.c

3507

{ SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },

arch/arm64/kvm/sys_regs.c

3509

{ SYS_DESC(SYS_ACCDATA_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3511

{ SYS_DESC(SYS_SCXTNUM_EL1), undef_access },

arch/arm64/kvm/sys_regs.c

3513

{ SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},

arch/arm64/kvm/sys_regs.c

3515

{ SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },

arch/arm64/kvm/sys_regs.c

3516

{ SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1,

arch/arm64/kvm/sys_regs.c

3519

{ SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },

arch/arm64/kvm/sys_regs.c

3526

{ SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility },

arch/arm64/kvm/sys_regs.c

3527

{ SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility },

arch/arm64/kvm/sys_regs.c

3571

{ SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0,

arch/arm64/kvm/sys_regs.c

3573

{ SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },

arch/arm64/kvm/sys_regs.c

3574

{ SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },

arch/arm64/kvm/sys_regs.c

3575

{ SYS_DESC(SYS_TPIDR2_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3577

{ SYS_DESC(SYS_SCXTNUM_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3579

{ SYS_DESC(SYS_AMCR_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3580

{ SYS_DESC(SYS_AMCFGR_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3581

{ SYS_DESC(SYS_AMCGCR_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3582

{ SYS_DESC(SYS_AMUSERENR_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3583

{ SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3584

{ SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3585

{ SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3586

{ SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },

arch/arm64/kvm/sys_regs.c

3652

{ SYS_DESC(SYS_CNTPCT_EL0), .access = access_arch_timer,

arch/arm64/kvm/sys_regs.c

3654

{ SYS_DESC(SYS_CNTVCT_EL0), .access = access_arch_timer,

arch/arm64/kvm/sys_regs.c

3656

{ SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer },

arch/arm64/kvm/sys_regs.c

3657

{ SYS_DESC(SYS_CNTVCTSS_EL0), access_arch_timer },

arch/arm64/kvm/sys_regs.c

3658

{ SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },

arch/arm64/kvm/sys_regs.c

3662

{ SYS_DESC(SYS_CNTV_TVAL_EL0), access_arch_timer },

arch/arm64/kvm/sys_regs.c

3767

{ SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 },

arch/arm64/kvm/sys_regs.c

3778

{ SYS_DESC(SYS_SP_EL1), access_sp_el1},

arch/arm64/kvm/sys_regs.c

3781

{ SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi },

arch/arm64/kvm/sys_regs.c

3782

{ SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi },

arch/arm64/kvm/sys_regs.c

3783

{ SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi },

arch/arm64/kvm/sys_regs.c

3784

{ SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi },

arch/arm64/kvm/sys_regs.c

3786

{ SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 },

arch/arm64/kvm/sys_regs.c

3791

{ SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 },

arch/arm64/kvm/sys_regs.c

3804

{ SYS_DESC(SYS_MPAMHCR_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3805

{ SYS_DESC(SYS_MPAMVPMV_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3806

{ SYS_DESC(SYS_MPAM2_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3807

{ SYS_DESC(SYS_MPAMVPM0_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3808

{ SYS_DESC(SYS_MPAMVPM1_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3809

{ SYS_DESC(SYS_MPAMVPM2_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3810

{ SYS_DESC(SYS_MPAMVPM3_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3811

{ SYS_DESC(SYS_MPAMVPM4_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3812

{ SYS_DESC(SYS_MPAMVPM5_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3813

{ SYS_DESC(SYS_MPAMVPM6_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3814

{ SYS_DESC(SYS_MPAMVPM7_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3817

{ SYS_DESC(SYS_RVBAR_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3818

{ SYS_DESC(SYS_RMR_EL2), undef_access },

arch/arm64/kvm/sys_regs.c

3830

{ SYS_DESC(SYS_ICC_SRE_EL2), access_gic_sre },

arch/arm64/kvm/sys_regs.c

3833

{ SYS_DESC(SYS_ICH_VTR_EL2), access_gic_vtr },

arch/arm64/kvm/sys_regs.c

3834

{ SYS_DESC(SYS_ICH_MISR_EL2), access_gic_misr },

arch/arm64/kvm/sys_regs.c

3835

{ SYS_DESC(SYS_ICH_EISR_EL2), access_gic_eisr },

arch/arm64/kvm/sys_regs.c

3836

{ SYS_DESC(SYS_ICH_ELRSR_EL2), access_gic_elrsr },

arch/arm64/kvm/sys_regs.c

3861

{ SYS_DESC(SYS_CNTHP_TVAL_EL2), access_arch_timer },

arch/arm64/kvm/sys_regs.c

3865

{ SYS_DESC(SYS_CNTHV_TVAL_EL2), access_arch_timer, .visibility = cnthv_visibility },

arch/arm64/kvm/sys_regs.c

3869

{ SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 },

arch/arm64/kvm/sys_regs.c

3871

{ SYS_DESC(SYS_CNTP_TVAL_EL02), access_arch_timer },

arch/arm64/kvm/sys_regs.c

3872

{ SYS_DESC(SYS_CNTP_CTL_EL02), access_arch_timer },

arch/arm64/kvm/sys_regs.c

3873

{ SYS_DESC(SYS_CNTP_CVAL_EL02), access_arch_timer },

arch/arm64/kvm/sys_regs.c

3875

{ SYS_DESC(SYS_CNTV_TVAL_EL02), access_arch_timer },

arch/arm64/kvm/sys_regs.c

3876

{ SYS_DESC(SYS_CNTV_CTL_EL02), access_arch_timer },

arch/arm64/kvm/sys_regs.c

3877

{ SYS_DESC(SYS_CNTV_CVAL_EL02), access_arch_timer },

arch/arm64/kvm/sys_regs.c

4197

SYS_DESC(OP_##insn), \

arch/arm64/kvm/sys_regs.c

4202

{ SYS_DESC(SYS_DC_ISW), access_dcsw },

arch/arm64/kvm/sys_regs.c

4203

{ SYS_DESC(SYS_DC_IGSW), access_dcgsw },

arch/arm64/kvm/sys_regs.c

4204

{ SYS_DESC(SYS_DC_IGDSW), access_dcgsw },

arch/arm64/kvm/sys_regs.c

4214

{ SYS_DESC(SYS_DC_CSW), access_dcsw },

arch/arm64/kvm/sys_regs.c

4215

{ SYS_DESC(SYS_DC_CGSW), access_dcgsw },

arch/arm64/kvm/sys_regs.c

4216

{ SYS_DESC(SYS_DC_CGDSW), access_dcgsw },

arch/arm64/kvm/sys_regs.c

4217

{ SYS_DESC(SYS_DC_CISW), access_dcsw },

arch/arm64/kvm/sys_regs.c

4218

{ SYS_DESC(SYS_DC_CIGSW), access_dcgsw },

arch/arm64/kvm/sys_regs.c

4219

{ SYS_DESC(SYS_DC_CIGDSW), access_dcgsw },

arch/arm64/kvm/sys_regs.c

4633

{ SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },

arch/arm64/kvm/sys_regs.c

4634

{ SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },

arch/arm64/kvm/sys_regs.c

4716

{ SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer },

arch/arm64/kvm/sys_regs.c

4719

{ SYS_DESC(SYS_AARCH32_CNTVCT), access_arch_timer },

arch/arm64/kvm/sys_regs.c

4721

{ SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },

arch/arm64/kvm/sys_regs.c

4722

{ SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer },

arch/arm64/kvm/sys_regs.c

4723

{ SYS_DESC(SYS_AARCH32_CNTVCTSS), access_arch_timer },

arch/arm64/kvm/vgic-sys-reg-v3.c

374

SYS_DESC(SYS_ ## r), \

arch/arm64/kvm/vgic-sys-reg-v3.c

386

{ SYS_DESC(SYS_ICC_PMR_EL1),

arch/arm64/kvm/vgic-sys-reg-v3.c

388

{ SYS_DESC(SYS_ICC_BPR0_EL1),

arch/arm64/kvm/vgic-sys-reg-v3.c

390

{ SYS_DESC(SYS_ICC_AP0R0_EL1),

arch/arm64/kvm/vgic-sys-reg-v3.c

392

{ SYS_DESC(SYS_ICC_AP0R1_EL1),

arch/arm64/kvm/vgic-sys-reg-v3.c

394

{ SYS_DESC(SYS_ICC_AP0R2_EL1),

arch/arm64/kvm/vgic-sys-reg-v3.c

396

{ SYS_DESC(SYS_ICC_AP0R3_EL1),

arch/arm64/kvm/vgic-sys-reg-v3.c

398

{ SYS_DESC(SYS_ICC_AP1R0_EL1),

arch/arm64/kvm/vgic-sys-reg-v3.c

400

{ SYS_DESC(SYS_ICC_AP1R1_EL1),

arch/arm64/kvm/vgic-sys-reg-v3.c

402

{ SYS_DESC(SYS_ICC_AP1R2_EL1),

arch/arm64/kvm/vgic-sys-reg-v3.c

404

{ SYS_DESC(SYS_ICC_AP1R3_EL1),

arch/arm64/kvm/vgic-sys-reg-v3.c

406

{ SYS_DESC(SYS_ICC_BPR1_EL1),

arch/arm64/kvm/vgic-sys-reg-v3.c

408

{ SYS_DESC(SYS_ICC_CTLR_EL1),

arch/arm64/kvm/vgic-sys-reg-v3.c

410

{ SYS_DESC(SYS_ICC_SRE_EL1),

arch/arm64/kvm/vgic-sys-reg-v3.c

412

{ SYS_DESC(SYS_ICC_IGRPEN0_EL1),

arch/arm64/kvm/vgic-sys-reg-v3.c

414

{ SYS_DESC(SYS_ICC_IGRPEN1_EL1),