SYSTEM_CONTROL_REG_BASE

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#define MUX_MODE_CTRL (SYSTEM_CONTROL_REG_BASE + 0x00)

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#define INTERNAL_RST (SYSTEM_CONTROL_REG_BASE + 0x04)

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#define PERIPHERAL_CTRL (SYSTEM_CONTROL_REG_BASE + 0x08)

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#define GPIO_0to7_CTRL (SYSTEM_CONTROL_REG_BASE + 0x0C)

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#define GPIO_8to15_CTRL (SYSTEM_CONTROL_REG_BASE + 0x10)

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#define GPIO_16to24_CTRL (SYSTEM_CONTROL_REG_BASE + 0x14)

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#define GPIO_INT_SRC_CFG (SYSTEM_CONTROL_REG_BASE + 0x18)

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#define SYS_BUF_STATUS (SYSTEM_CONTROL_REG_BASE + 0x1C)

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#define PCIE_IP_REG_ACS (SYSTEM_CONTROL_REG_BASE + 0x20)

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#define PCIE_IP_REG_ACS_ADDR (SYSTEM_CONTROL_REG_BASE + 0x24)

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#define PCIE_IP_REG_ACS_DATA (SYSTEM_CONTROL_REG_BASE + 0x28)