TA
pcsr = __raw_readw(TA(MCFPIT_PCSR));
__raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
pcntr = __raw_readw(TA(MCFPIT_PCNTR));
__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
__raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR));
MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
__raw_writew(delta, TA(MCFPIT_PMR));
scnt = __raw_readl(TA(MCFSLT_SCNT));
if (__raw_readl(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) {
scnt = __raw_readl(TA(MCFSLT_SCNT));
__raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
TA(MCFSLT_SCR));
__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
__raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
__raw_writetrr(mcftmr_cycles_per_jiffy - 1, TA(MCFTIMER_TRR));
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
__raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
tcn = __raw_readw(TA(MCFTIMER_TCN));
set = TA(timings->ta) | RHOLD(timings->rhold) | RSTROBE(timings->rstrobe) |
#define TA_VAL(x) (((x) & TA(TA_MAX)) >> TA_SHIFT)
#define TIMINGS_MASK (TA(TA_MAX) | \
gem_writel(bp, TA, adj);
gem_writel(bp, TA, 0);
gem_writel(bp, TA, 0);
case TA:
TA,TB,TS,TB
mib->fddiPORTNeighborType = TA ;
case TA :
((policy & POLICY_AA) && ne == TA) ||
((policy & POLICY_BA) && ne == TA) ||
((policy & POLICY_SA) && ne == TA) ||
((policy & POLICY_MA) && ne == TA) ||
if ( (type == TA && ne == TA ) ||
(type == TA && ne == TS ) ||
(type == TS && ne == TA ) ||
mib->fddiPORTMy_Type = (np == PA) ? TA :
mib->fddiPORTMy_Type = (np == PB) ? TB : TA ;
case TA :
static void tkip_mixing_phase1(u16 * TTAK, const u8 * TK, const u8 * TA,
TTAK[2] = Mk16(TA[1], TA[0]);
TTAK[3] = Mk16(TA[3], TA[2]);
TTAK[4] = Mk16(TA[5], TA[4]);