T4
static const u32 T4[256] = {
K0 = T4[(kappa[N - 1] >> 24) ];
K1 = T4[(kappa[N - 1] >> 16) & 0xff];
K2 = T4[(kappa[N - 1] >> 8) & 0xff];
K3 = T4[(kappa[N - 1] ) & 0xff];
K0 = T4[(kappa[i] >> 24) ] ^
K1 = T4[(kappa[i] >> 16) & 0xff] ^
K2 = T4[(kappa[i] >> 8) & 0xff] ^
K3 = T4[(kappa[i] ) & 0xff] ^
T0[T4[(v >> 24) ] & 0xff] ^
T1[T4[(v >> 16) & 0xff] & 0xff] ^
T2[T4[(v >> 8) & 0xff] & 0xff] ^
T3[T4[(v ) & 0xff] & 0xff];
static const u64 T4[256] = {
T4[(int)(K1 >> 24) & 0xff] ^
T4[(int)S[(int)(K1 >> 24) & 0xff] & 0xff] ^
T4[(int)(state >> 24) & 0xff] ^
(T4[(int)(state >> 24) & 0xff] & 0x00000000ff000000ULL) ^
case T4:
case T4:
data->dev_type = T4;
.fw_ver = __cpu_to_be32(FW_VERSION(T4)),
.intfver_nic = FW_INTFVER(T4, NIC),
.intfver_vnic = FW_INTFVER(T4, VNIC),
.intfver_ri = FW_INTFVER(T4, RI),
.intfver_iscsi = FW_INTFVER(T4, ISCSI),
.intfver_fcoe = FW_INTFVER(T4, FCOE),
ASPEED_PINCTRL_PIN(T4),
SSSF_PIN_DECL(T4, GPIOJ4, VGAHS, SIG_DESC_SET(SCU84, 12));
ASPEED_PINCTRL_PIN(T4),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V2, T4, SCU8C, 29),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V2, T4, SCU8C, 29),
SIG_EXPR_LIST_DECL_SINGLE(T4, VPIG7, VPI24, VPI24_DESC, T4_DESC);
SIG_EXPR_LIST_DECL_SINGLE(T4, PWM7, PWM7, T4_DESC, COND2);
PIN_DECL_2(T4, GPION7, VPIG7, PWM7);
FUNC_GROUP_DECL(PWM7, T4);
U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5,
#define DES_PC2(a, b, c, d) (T4(d) | T3(c) | T2(b) | T1(a))