SZ_8
#define TEGRA_TMR1_SIZE SZ_8
#define TEGRA_TMR2_SIZE SZ_8
#define TEGRA_TMR3_SIZE SZ_8
#define TEGRA_TMR4_SIZE SZ_8
#define DMA_BURSTL_8DW SZ_8
return ALIGN_DOWN(ast->vram_size - size, SZ_8);
pitch = args->width * DIV_ROUND_UP(args->bpp, SZ_8);
pitch_align = DIV_ROUND_UP(args->bpp, SZ_8) * 8;
pitch_align = round_up(args->width, 32) * DIV_ROUND_UP(args->bpp, SZ_8);
ret = drm_mode_size_dumb(dev, args, SZ_8, 0);
KUNIT_ASSERT_EQ(test, SZ_8, pf_profile_fair_dbs(gt, num_vfs));
return (id < (npg * psz / (esz * SZ_8)));
idx = id >> ilog2(psz / (esz * SZ_8));
epp = psz / (esz * SZ_8);
npg = DIV_ROUND_UP(nl2 * SZ_8, psz);
#define PINS_PER_GROUP SZ_8
#define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n)
#define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n)
r1.size = SZ_8;
ASSERT_LE(SZ_8, req_node->size);
ASSERT_LE(SZ_8, req_node->size);
min_addr = memblock_end_of_DRAM() - SZ_8;
ASSERT_LE(SZ_8, req_node->size);
ASSERT_LE(SZ_8, req_node->size);
memblock_reserve(memblock_start_of_DRAM() + SZ_16 * i, SZ_8);
memblock_reserve(memblock_start_of_DRAM() + memblock_phys_mem_size() / 2 - SZ_8,