SZ_128K
#define SRAM_SIZE SZ_128K
.sram_len = SZ_128K,
#define LPC32XX_IRAM_BANK_SIZE SZ_128K
.size = SZ_128K,
.size = SZ_128K,
.offset = SZ_128K,
.size = SZ_128K,
.size = SZ_128K,
.size = SZ_2M - 2 * SZ_128K,
#define OMAP1_DSPREG_SIZE SZ_128K
.size = SZ_128K,
[0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_128K),
BUG_ON(offset < -SZ_128K || offset >= SZ_128K);
if ((imm & 3) || imm < -SZ_128K || imm >= SZ_128K) {
if ((imm & 3) || imm < -SZ_128K || imm >= SZ_128K) {
if ((imm & 3) || imm < -SZ_128K || imm >= SZ_128K) {
#define PCI_PORT_BASE _AC(0xc000000000000000 + SZ_128K, UL)
FIX_EARLY_DEBUG_BASE = FIX_EARLY_DEBUG_TOP+(ALIGN(SZ_128K, PAGE_SIZE)/PAGE_SIZE)-1,
RTAS_WORK_AREA_MAX_ALLOC_SZ = SZ_128K,
#define USER_TOP ((ASM_CONST(CONFIG_PAGE_OFFSET) - SZ_128K) & ~(UL(SZ_128K) - 1))
unsigned long top = ALIGN((unsigned long)_etext - PAGE_OFFSET, SZ_128K);
if (k_size < SZ_128K)
.size = (2 * SZ_128K),
.size = (20 * SZ_128K),
CACHE_ENTRY(0x39, CACHE_L2, SZ_128K ), /* 4-way set assoc, sectored cache, 64 byte line size */
CACHE_ENTRY(0x3b, CACHE_L2, SZ_128K ), /* 2-way set assoc, sectored cache, 64 byte line size */
CACHE_ENTRY(0x41, CACHE_L2, SZ_128K ), /* 4-way set assoc, 32 byte line size */
CACHE_ENTRY(0x79, CACHE_L2, SZ_128K ), /* 8-way set assoc, sectored cache, 64 byte line size */
#define GAUDI2_CB_POOL_CB_SIZE SZ_128K /* 128KB */
#define QAIC_DBC_BASE SZ_128K
return SZ_128K;
#define BINDER_MMAP_SIZE SZ_128K
#define SUN4I_NDMA_MAX_SEG_SIZE SZ_128K
return single_open_size(file, debugfs_show, file, SZ_128K);
if (args->stream_size > SZ_128K || args->nr_relocs > SZ_128K ||
args->nr_bos > SZ_128K || args->nr_pmrs > 128) {
#define I915_GEM_STOLEN_BIAS SZ_128K
.size = SZ_128K,
#define GEN9_GUC_FW_RESERVED SZ_128K
BUILD_BUG_ON(OA_BUFFER_SIZE < SZ_128K || OA_BUFFER_SIZE > SZ_16M);
.gmem = SZ_128K,
.gmem = SZ_128K,
.gmem = SZ_128K,
.gmem = SZ_128K,
.gmem = (SZ_128K + SZ_8K),
.gmem = (SZ_128K + SZ_8K),
.gmem = (SZ_128K + SZ_8K),
.gmem = SZ_1M + SZ_128K,
.gmem = SZ_128K,
.gmem = (SZ_128K + SZ_4K),
.gmem = (SZ_128K + SZ_4K),
chunk_size < SZ_128K || chunk_size > SZ_8M)
#define CTB_G2H_BUFFER_SIZE (SZ_128K)
if (!is_power_of_2(value) || value < SZ_128K || value > SZ_128M) {
offset = round_up(offset, SZ_128K); /* SW must round up to nearest 128K */
cpmem->base = devm_ioremap(dev, base, SZ_128K);
.qplimit = SZ_128K,
(SZ_4K | SZ_8K | SZ_16K | SZ_32K | SZ_64K | SZ_128K | SZ_256K | \
return SZ_128K;
#define TEGRA241_VINTFi_PAGE0(i) (TEGRA241_VINTF_PAGE_BASE + SZ_128K*(i))
#define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K);
base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K;
its->vlpi_redist_offset = SZ_128K;
its->sgir_base = ioremap(its->phys_base + SZ_128K, SZ_64K);
#define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
val = gicr_read_vpendbaser(ptr + SZ_128K + GICR_VPENDBASER);
ptr + SZ_128K + GICR_VPENDBASER);
val = gicr_read_vpropbaser(ptr + SZ_128K + GICR_VPROPBASER);
gicr_write_vpropbaser(val, ptr + SZ_128K + GICR_VPROPBASER);
alt = ioremap(cpuif_res.start, SZ_128K);
cpuif_res.end = cpuif_res.start + SZ_128K -1;
if (resource_size(&cpuif_res) == SZ_128K) {
fmt->sizeimage[i] = clamp_val(fmt->sizeimage[i], SZ_128K, SZ_8M);
fmt->sizeimage[0] = clamp_val(pixmp->plane_fmt[0].sizeimage, SZ_128K, SZ_8M);
.dma_size[DMA_DSCR_HOST] = SZ_128K, \
.dma_size[DMA_DSCR_DEVICE] = SZ_128K, \
boot_sectors_num = card->ext_csd.raw_boot_mult * SZ_128K /
SZ_128K / 512, SZ_256K / 512, SZ_512K / 512, SZ_1M / 512,
mmc->max_req_size = SZ_128K;
.size = SZ_128K,
memorg->pages_per_eraseblock = (SZ_128K << tmp) /
mtd->erasesize = SZ_128K << tmp;
SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
SZ_2K, SZ_512, SZ_128K, 0, 5, 128, NAND_ECC_INFO(8, SZ_512) },
.size = SZ_128K,
.size = SZ_128K,
.sector_size = SZ_128K,
.size = SZ_128K,
.sector_size = SZ_128K,
.size = SZ_128K,
.size = SZ_128K,
.size = SZ_128K,
.size = SZ_128K,
.size = SZ_128K,
#define NFP_ARM_MPCORE_SIZE SZ_128K
#define LABEL_AREA_SIZE SZ_128K
WARN(priv->data_len > SZ_128K, "Unexpected (big) NVRAM size: %zu B\n", priv->data_len);
SZ_128K);
SZ_128K);
lane->ctrl_off = SZ_128K;
.macro_size = SZ_128K,
.macro_size = SZ_128K,
#define ADI_15BIT_SLAVE_ADDR_SIZE SZ_128K
#define SIZE_WORKSPACE SZ_128K
/ SZ_128K;
#define GET_QUOTE_BUF_SIZE SZ_128K
if (size <= SZ_128K)
#define BTRFS_MAX_COMPRESSED (SZ_128K)
#define BTRFS_MAX_UNCOMPRESSED (SZ_128K)
nread_max = SZ_128K;
reada_max = (*level == 1 ? SZ_128K : eb->fs_info->nodesize);
if (em->start != SZ_128K) {
ret = test_add_free_space_entry(cache, SZ_128M - SZ_256K, SZ_128K, 0);
if (!test_check_exists(cache, SZ_128M - SZ_256K, SZ_128K)) {
ret = btrfs_add_free_space(cache, SZ_128M - SZ_128K, SZ_128K);
if (!test_check_exists(cache, SZ_128M - SZ_128K, SZ_128K)) {
ret = test_add_free_space_entry(cache, SZ_128M + SZ_128K, SZ_128K, 0);
if (!test_check_exists(cache, SZ_128M + SZ_128K, SZ_128K)) {
ret = btrfs_add_free_space(cache, SZ_128M, SZ_128K);
if (!test_check_exists(cache, SZ_128M, SZ_128K)) {
#define VM_READAHEAD_PAGES (SZ_128K / PAGE_SIZE)
unsigned long pages = totalram_pages() / (SZ_1G / SZ_128K);
atomic_pool_size = max_t(size_t, pages << PAGE_SHIFT, SZ_128K);
#define RES_TEST_CODE_OFFSET (RES_TEST_RAM2_OFFSET + SZ_128K)
#define RES_TEST_CODE_SIZE SZ_128K
sysctl_user_reserve_kbytes = min(free_kbytes / 32, SZ_128K);
if (tmp > 0 && tmp < SZ_128K)
if (done - *flushed_at < SZ_128K && tcp_inq(sk) > max_rec)
#define AVS_CL_DEFAULT_BUFFER_SIZE SZ_128K
#define SPRD_COMPR_MAX_FRAGMENT_SIZE SZ_128K
#define LSA_SIZE SZ_128K
.base = SZ_128K,
.size = SZ_128K
.base = SZ_128K,
.size = SZ_128K
phys_addr_t memory_base = SZ_128K;
#define MEMORY_BASE(idx) (SZ_128K + (MEM_SIZE * 2) * (idx))
LABEL_SIZE = SZ_128K,
LABEL_SIZE = SZ_128K,
.config_size = SZ_128K,
|| cmd.cfg_size.config_size != SZ_128K