SZ_128
DEFINE_RES_MEM(CLPS711X_PHYS_BASE + HALT, SZ_128);
tdev->device.max_burst = SZ_128;
#define MV_XOR_MIN_BYTE_COUNT SZ_128
char name[SZ_128];
KUNIT_ASSERT_EQ(test, SZ_128, pf_profile_fair_dbs(gt, num_vfs));
.qplimit = SZ_128,
#define ENCODER_STREAM_OFFSET SZ_128
SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
#define ADMIN_SQE_SIZE SZ_128
#define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
mask = (roundup_pow_of_two(size) / SZ_128) - 1;
.rxfifo = SZ_128,
.rxfifo = SZ_128,
.rxfifo = SZ_128,
.rxfifo = SZ_128,
.rxfifo = SZ_128,
.rxfifo = SZ_128,
.rxfifo = SZ_128,
#define DMA_PORT_CSS_MAX_SIZE SZ_128
phys_addr_t r2_size = SZ_128;
r1.size = SZ_128;
r2.size = SZ_128;
r2.base = next_node->base + SZ_128;
min_addr = memblock_start_of_DRAM() + SZ_128;
phys_addr_t size = SZ_128;
r1.size = SZ_128;
r2.size = SZ_128;
r2.base = next_node->base + SZ_128;
phys_addr_t r1_size = SZ_128;
phys_addr_t r2_size = SZ_128;
r2.size = SZ_128;
r2.size = SZ_128;
r2.size = SZ_128;
phys_addr_t size = SZ_128;
phys_addr_t size = SZ_128;
phys_addr_t size = SZ_128;
r2.size = SZ_128;
r2.size = SZ_128;