SW_RESET
if (sc->flags & SW_RESET) {
.flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
.flags = CLAMP_IO | AON_RESET | SW_RESET,
.flags = CLAMP_IO | AON_RESET | SW_RESET,
.flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
.flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
.flags = CLAMP_IO | SW_RESET | VOTABLE,
.flags = CLAMP_IO | SW_RESET | AON_RESET,
.flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
.flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
.flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
val |= SW_RESET;
val &= ~SW_RESET;
ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
SW_RESET);
qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
qphy_clrbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
priv->mode = SW_RESET;
regmap_update_bits(admaif->regmap, reset_reg, SW_RESET_MASK, SW_RESET);
!(val & SW_RESET_MASK & SW_RESET),