drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1060

SW_MODE, &s->sw_mode);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

157

SW_MODE, info->gfx9.swizzle,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

526

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

290

HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

488

type SW_MODE;\

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1297

SW_MODE, &s->sw_mode);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

322

SW_MODE, info->gfx9.swizzle,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

414

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

331

SW_MODE, info->gfx9.swizzle,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

342

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

70

HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

54

HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

565

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

592

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx_addr3.swizzle);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

982

SW_MODE, &s->sw_mode);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

65

HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\

drivers/mtd/devices/spear_smi.c

231

writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1);

drivers/mtd/devices/spear_smi.c

389

writel(ctrlreg1 & ~SW_MODE, dev->io_base + SMI_CR1);

drivers/mtd/devices/spear_smi.c

461

writel((ctrlreg1 | SW_MODE) & ~WB_MODE, dev->io_base + SMI_CR1);

drivers/mtd/devices/spear_smi.c

577

val &= ~(SW_MODE | WB_MODE);

drivers/mtd/devices/spear_smi.c

635

writel((ctrlreg1 | WB_MODE) & ~SW_MODE, dev->io_base + SMI_CR1);

drivers/mtd/devices/spear_smi.c

759

writel(val | SW_MODE, dev->io_base + SMI_CR1);

drivers/mtd/devices/spear_smi.c

784

writel(val & ~SW_MODE, dev->io_base + SMI_CR1);

sound/soc/qcom/lpass-hdmi.c

113

ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->hw_chs_sel, SW_MODE);

sound/soc/qcom/lpass-hdmi.c

121

ret = regmap_field_write(drvdata->hdmi_tx_dmactl[0]->hw_usr_sel, SW_MODE);