SW
#define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
#define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
#define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
if (flags & SW) {
#define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
#define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
#define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
.flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
CASE(SW );
case RM_ENGINE_TYPE( SW, SW, 0);
case RM_ENGINE_TYPE( SW, SW, 0);
INPUT_DEV_CAP_ATTR(SW, sw);
INPUT_CLEANSE_BITMASK(dev, SW, sw);
AXP_DESC_SW(AXP806, SW, "sw", "swin",
AXP_DESC_SW(AXP809, SW, "sw", "swin",
AXP_DESC_SW(AXP813, SW, "sw", "swin",
AXP_DESC_SW(AXP15060, SW, "sw", NULL,
MC13xxx_DEFINE(SW, _name, _node, _reg, _vsel_reg, _voltages, ops)