SVC_I3C_MSTATUS
writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
mstatus = readl(master->regs + SVC_I3C_MSTATUS);
writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
writel(SVC_I3C_MINT_COMPLETE, master->regs + SVC_I3C_MSTATUS);
readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
mstatus = readl(master->regs + SVC_I3C_MSTATUS);
readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg,
ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS)) &&
return readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg,
ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg,
writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
ret = readl_relaxed_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, val,
status = readl(master->regs + SVC_I3C_MSTATUS);
u32 active = readl(master->regs + SVC_I3C_MSTATUS);
writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,