drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

533

for (svc = 0; svc < SVC_BASE_COUNT; svc++) {

drivers/crypto/intel/qat/qat_common/adf_cfg_services.h

19

SVC_DCC = SVC_BASE_COUNT,

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

573

for (i = 0; i < SVC_BASE_COUNT; i++)

drivers/crypto/intel/qat/qat_common/adf_rl.c

548

if (svc >= SVC_BASE_COUNT)

drivers/crypto/intel/qat/qat_common/adf_rl.c

59

if (sla_in->srv >= SVC_BASE_COUNT) {

drivers/crypto/intel/qat/qat_common/adf_rl.c

702

for (i = 0; i < SVC_BASE_COUNT; i++) {

drivers/crypto/intel/qat/qat_common/adf_rl.c

717

for (i = 0; i < SVC_BASE_COUNT; i++) {

drivers/crypto/intel/qat/qat_common/adf_rl.c

958

if (srv >= SVC_BASE_COUNT)

drivers/crypto/intel/qat/qat_common/adf_rl.h

93

u32 svc_ae_mask[SVC_BASE_COUNT];

drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c

286

if (get == SVC_BASE_COUNT)

drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c

451

data->cap_rem_srv = SVC_BASE_COUNT;

drivers/crypto/intel/qat/qat_common/adf_sysfs_rl.c

452

data->input.srv = SVC_BASE_COUNT;