arch/sh/kernel/cpu/sh2/setup-sh7619.c

201

__raw_writeb(__raw_readb(STBCR3) & ~0x10, STBCR3);

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

100

[MSTP32] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 2, 0), /* ADC */

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

101

[MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

97

[MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

98

[MSTP34] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 4, 0), /* SDHI0 */

arch/sh/kernel/cpu/sh2a/clock-sh7264.c

99

[MSTP33] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 3, 0), /* SDHI1 */

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

133

[MSTP35] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 5, 0), /* MTU2 */

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

134

[MSTP32] = SH_CLK_MSTP8(&peripheral1_clk, STBCR3, 2, 0), /* ADC */

arch/sh/kernel/cpu/sh2a/clock-sh7269.c

135

[MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */

arch/sh/kernel/cpu/sh2a/setup-sh7201.c

414

__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);

arch/sh/kernel/cpu/sh2a/setup-sh7203.c

351

__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);

arch/sh/kernel/cpu/sh2a/setup-sh7206.c

287

__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);