drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h

80

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h

81

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h

87

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h

79

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h

87

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

87

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

90

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

93

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

93

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

92

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

92

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

91

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

92

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h

91

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

80

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h

80

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

79

.name = "sspp_3", .id = SSPP_VIG3,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

202

case SSPP_VIG3:

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

492

[SSPP_VIG3] = { { 0, 26, 6 }, { 3, 12 } },

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

255

} else if (pipe >= SSPP_VIG0 && pipe <= SSPP_VIG3) {

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

204

status->sspp[SSPP_VIG3] = (value >> 10) & 0x1;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

92

status->sspp[SSPP_VIG3] = (value >> 10) & 0x3;

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

198

[SSPP_VIG2] = 7, [SSPP_VIG3] = 19,

drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

450

[SSPP_VIG2] = 7, [SSPP_VIG3] = 19,

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

289

case SSPP_VIG3: return MDP5_CTL_LAYER_REG_VIG3(stage);

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

312

case SSPP_VIG3: return MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3;

drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c

440

case SSPP_VIG3: return MDP5_CTL_FLUSH_VIG3;

drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

610

SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,