drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

425

sspp_idx - SSPP_NONE,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

487

[SSPP_NONE] = { { -1 }, { -1 } },

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

281

for (i = SSPP_NONE; i < SSPP_MAX; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h

134

uint32_t sspp_to_crtc_id[SSPP_MAX - SSPP_NONE];

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1954

SSPP_NONE);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

372

ot_params.num = pipe->sspp->idx - SSPP_NONE;

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

1043

for (i = SSPP_NONE + 1; i < ARRAY_SIZE(global_state->sspp_to_crtc_id); i++)

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

194

rm->hw_sspp[sspp->id - SSPP_NONE] = hw;

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

125

return rm->hw_sspp[sspp_idx - SSPP_NONE];

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

39

struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

227

enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };

drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c

228

enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

960

return SSPP_NONE;

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

970

return SSPP_NONE;