STM32F7_I2C_CR1
writel_relaxed(cr1, base + STM32F7_I2C_CR1);
cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
writel_relaxed(cr1, base + STM32F7_I2C_CR1);
stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP);
stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP);
stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
i2c_dev->base + STM32F7_I2C_CR1);
stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
writel_relaxed(cr1, base + STM32F7_I2C_CR1);
cr1 = readl_relaxed(base + STM32F7_I2C_CR1);